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DesignCon 2015

Date: Jan. 28-29, 2015.
Location: Santa Clara.

Xpeedic Technology, Inc. will exhibit at DesignCon 2015 at Santa Clara on Jan. 28-29, 2015.

Xpeedic will showcase their high speed signal integrity (SI) solution and RF front end miniaturization solution in the conference. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.

Please visit Xpeedic at Booth #912 to find out more.

website: http://www.designcon.com/

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ICCAD 2014

Date:Dec. 11-12, 2014.

Location: Hong Kong

Xpeedic Technology, Inc. will exhibit at CSIA-ICCAD 2014 Annual Conference at Hong Kong on Dec. 11-12, 2014.
At Dec 12, Dr.Wenliang Dai, Engineering VP, will present the leading design method-“RFSiP Miniaturization by Integrated Passive Devices(IPD)” with IC industry companion in ICCAD Subject Forum 3.
At booth 1F#21-22,Xpeedic will showcase their high speed signal integrity (SI) solution and RF front end miniaturization solution in the conference. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.

The conference official  website:
http://www.csia-iccad.net.cn/
http://www.cicmag.com/bbx/856303-856303.html

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Asian IBIS Summit (Shanghai)

Data:  Friday, Nov. 14, 2014.
Location:  Parkyard Hotel Shanghai, 699 Bibo Road, Zhangjiang Hi-Tech Park, Shanghai 201203, P.R. China

Xpeedic Technology, Inc. will participate the Asian IBIS Summit (Shanghai) on Nov. 14, 2014. Dr. Wenliang Dai, VP of Engineering of Xpeedic Technology, Inc.,  will deliver the following speech.
Paper:     Connector Via Footprint Optimization for 25Gbps Channel Design
Authors:  Wenliang Dai and Zhouxiang Su
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Xpeedic Announces Release of SnpExpert and ViaExpert 2014.02

Suzhou, China. —Sep. 30, 2014 —Xpeedic today unveils two enhanced solution in the area of high speed signal integrity: SnpExpert and ViaExpert version 2014.02.

SnpExpert enables SI engineers to quickly explore the S-parameters in both frequency domain and time domain. SnpExpert 2014.02 solution provides quick single-ended and differential pair plot with PLTS style, enhanced TDR plot and built-in delay and skew calculator,  improved  S-parameter passivity/causality/reciprocity/stability analyzer,  built-in IEEE and OIF compliance, customized report generator in Word/PPT/Html format and one-click-for-all template plot

ViaExpert enables fast and accurate via modeling and simulation. In the latest release of ViaExpert, both 3D FEM solver and fast hybrid solver are deployed to achieve fast and accurate simulation.  In addition, ViaExpert 2014.02 release provides enhanced multi-core simulation performance, improved built-in connector footprint database, via array template, SMA model for quick pre-layout analysis and Allegro brd import for post-layout analysis. The customized parametric analysis is also supported in the new release.

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EPEPS 2014

Date:Oct 26-29, 2014.

Location: Portland, Oregon

Xpeedic Technology, Inc. will exhibit at EPEPS 2014 Portand, Oregon on Oct 26-29, 2014. Xpeedic will showcase EDA software, IPD and SiP solution. The EDA software tools enables fast electromagnetic modeling and extraction. The IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.
More details to see http://www.epeps.org/

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SMIC 2014 Technology Symposium in Shanghai

Date: Sept. 18, 2014.

Location: Shanghai

Xpeedic will be exhibiting at the SMIC 2014 Technology Symposium in Shanghai on Sept, 18, 2014. As a RF EDA and IP vendor, Xpeedic will showcase its flagship RFIC/TSV EDA tools, IPD(Integrated Passive Device) IP, and SiP package design services. Please visit us at Booth #08 to find out more.

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Xpeedic Announces Release of IRIS Platform Version 2014.01

Suzhou, China. -Jul. 30, 2014 -Xpeedic today releases three enhanced solutions (IRIS, iModeler and iVerifier) under IRIS platform version 2014.01 which will greatly accelerate RFIC passive extraction, PDK model generation and verification.  In the latest release of IRIS platform,  the mesh and solver technologies are further improved along with the new features such as auto HFSS project export and frequency and temperature dependent material support.

IRIS 2014.01 solution helps RFIC designers to quickly simulate the passives and interconnects of interest and then verify the design by automatically back-annotating the EM simulation to schematic. The solution greatly helps RFIC designers to reduce the design cycle and achieve first-pass silicon success.

iModeler 2014.01 solution accelerates the PDK model generation by built-in parameterized layout for passive devices and fast IRIS mesh and solver technologies.

iVerifier 2014.01 solution enables users to assess the PDK model quality by sweeping the parameters and evaluating the key metrics of the PDK elements.

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IMS 2014

Date:June 1-6, 2014.

Location: Florida

Xpeedic Technology, Inc. will exhibit at IMS 2014 in Tampa Bay, Florida on June 1-6, 2014. Xpeedic will showcase their EDA software, IPD and SiP solution in the area of radio frequency integrated circuits, or RFICs. Their EDA software tools IRIS, iModeler, iVerifier, seamlessly integrated with Cadence Virtuoso, enables fast electromagnetic modeling and extraction for RFIC designers and PDK engineers. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Visit Xpeedic at Booth #101 to find out more.

More details to see http://www.ims2014.org/

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Xpeedic to Exhibit at IWS2014

Xpeedic Technology, Inc. will exhibit at IWS2014 in Xi’an on March 24-26, 2014. Xpeedic will showcase their EDA software, IPD and SiP solution in the area of radio frequency integrated circuits, or RFICs. Their EDA software tools IRIS, iModeler, iVerifier, seamlessly integrated with Cadence Virtuoso, enables fast electromagnetic modeling and extraction for RFIC designs. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Visit Xpeedic at Booth #4024 to find out more.

More details to see http://iws-ieee.org/

DesignCon2014-Banner

Xpeedic to Exhibit at DesignCon 2014

Xpeedic Technology, Inc. will exhibit at DesignCon 2014 at Santa Clara on Jan. 28-31, 2014. Xpeedic will showcase their EDA software and System-in-Package (SiP) design service in the conference.

Xpeedic will bring fast and accurate signal integrity software for IC-package-system designs. ViaExpert enables fast via modeling and simulation for both pre-layout and post-layout scenarios. SnpExpert provides quick way to view S-parameter and the associated TDR. Hermes tool provides signal and power integrity simulation for complex IC-package-board designs including thru-silicon-via (TSV).

Xpeedic’s SiP design service enables customers to achieve system miniaturization by integrating ICs from different process into one package. Their IP on silicon integrated passive devices (IPD) empowers further miniaturization by integrating the peripheral passives for a broad range of RF applications.

Please visit Xpeedic at Booth #755 to find out more.