Xpeedic Technology, Inc. will host an EDA seminar in Taipei, Taiwan on Oct.12, 2015.
High speed communication link design becomes more and more challenging because of the ever increasing data rate and the rapid development of semiconductor and IC technology. At multi-gigabit per second data rate, designers must characterize all the pieces in the signal path from transmit to receiver to address the signal integrity issues, including reflections, crosstalk, Simultaneous Switching Noise (SSN) and so on. Even a small discontinuity can significantly degrade the signal.
This seminar is targeting the SI engineers and to discuss fast and accurate way to model and simulate discontinuities along the path and optimize the channel performance. Xpeedic’s co-founder CEO Dr.Ling and VP engineering Dr. Dai will present within the seminar.
9:30-9:40 Welcome and Overview
9:40-10:10 S-parameter in high speed SI
10:10-10:40 Via modeling and optimization
10:40-11:00 Coffee/tea break
11:00-11:30 Impedance discontinuities from surface mounted pads
11:30-12:00 High speed channel modeling and optimization
12:00-13:00 Luck draw and Lunch
Venue: Conference center of National Taipei University of Technology
If you have interest, please send email to Marketing@xpeedic.com for registration.