designcon2018-2

DesignCon 2018

Please Join Us in Santa Clara for DesignCon 2018

This is your exclusive invitation to attend the largest meeting of chip, board, and systems design engineers with a complimentary Expo Pass or a 20% discount on Conference Packages! Now in its 23rd year, DesignCon offers high-caliber content, rich technical education, and in-depth training – all created by engineers for engineers.

This special discount comes to you courtesy of:

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Visit us at Booth #1034 

Register now and save 20% on your choice of an All-Access or 2-Day Pass by using this promo code EXD-EprTiC17 — or claim your complimentary Expo Pass. Start the new year ahead of the rest.

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EDA培训--2018第1期

EDA 2018 Training Program Series


芯禾科技EDA培训系列课程

2018年第一期

尊敬的工程师伙伴,     

      感谢大家的厚爱,《芯禾科技EDA培训系列课程》在2017年开到了上海,开到了北京,开到了台北,获得了众多工程师的欢迎和期待。我们将竭尽所能,在2018年带来更多应景的内容,让更多地区的工程师能够获得福利。     
      2018年1月,我们针对华东的工程师安排了两场培训,课程将继续由芯禾科技的各位资深讲师领衔主讲。     
      本课程对购买了芯禾科技EDA工具的客户免费开放(每个License限报名两人),也欢迎其他有兴趣的工程师报名参加。    
      机会难得,强烈建议大家提前抢票和专家面对面交流!  

高速线缆及高速背板系统全通道建模与仿真

随着背板系统速率的不断提升,各大连接器厂家接连推出Cable代替PCB的解决方案,充分利用Cable损耗小、一致性高的优点来设计高速背板系统。本期课程,将分享如何对Cable进行建模仿真的解决方案,以及对于背板系统、如何进行整板全通道损耗分析。 

  • 适用对象:从事高速设计、信号完整性分析的工程师
  • 时间:2018112日 周五 10:00-15:30
  • 地点:祖冲之路2290弄展想广场1号楼1101室(近2号线广兰路站)
  • 培训费用:人民币1,000元,包括午餐、茶歇、配套软件及讲义等费用
  • 报名优惠:前十名报名成功的工程师,减免所有培训费用
  • 议程安排:

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射频芯片无源器件参数提取和建模

先进工艺下的无源结构建模、无源结构的仿真优化向来是射频芯片设计的热点,本期课程将针对“无源结构建模的技术、PDK标准库建立、无源器件优化及查找功能”等大家所关心的技术要点进行详细的剖析与交流。

  • 适用对象:从事射频芯片设计以及模拟、混合信号设计的工程师
  • 时间:2018年1月11日 周四 10:00-15:30
  • 地点:祖冲之路2290弄展想广场1号楼1101室(近2号线广兰路站)
  • 培训费用:人民币1,000元,包括午餐、茶歇、配套软件及讲义等费用
  • 报名优惠:前十名报名成功的工程师,减免所有培训费用
  • 议程安排:

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IPC PCB

2017 IPC PCB Technical Seminar in Shenzhen

时间:2017年12月7日(星期四)

地点:深圳会展中心5楼菊花厅

芯禾科技将于2017年12月7日参加在深圳举办的2017年IPC PCB可制造性设计专题研讨会。电子产品的品质首先取决于PCB设计,在PCB设计时有没有考虑到后续产品生产制造时面临的线路布局的合理性、工艺可实现性、可测试性、成本因素、生产的便捷性以及成品工作的环境、散热等问题,是电子产品设计好坏的关键因素。基于IPC在PCB设计和制造标准培训认证方面积累的最佳实践经验,IPC再次组织IPC设计师理事会及IPC会员单位于12月7日在深圳会展中心举办PCB可制造性设计专题研讨会,帮助中国的PCB设计师提高符合客户需要和企业制造能力的设计知识和技能。本次研讨会得到华为技术有限公司、苏州芯禾电子科技有限公司的大力支持。

同时,芯禾科技的联合创始人、工程副总裁代文亮博士也将在本次研讨会上发表题为《高速PCB设计中的S参数处理与高级去嵌技术》的演讲。具体时间段为7日上午10:15。

会议议程

如有兴趣,可点击这里进行报名。

汽车电子论坛

Automotive Electronics in Shanghai

日期:        2017年11月23日

时间:        9:30-16:30

地点:        上海长荣桂冠酒店

在汽车轻量小型化、智能化和电动化趋势的推动下,汽车电子的整体市场规模增长迅速,汽车电子行业将面临新的机遇。汽车电子行业的创新主要来自于三个方面:一是如何无缝地连接移动体验;二是如何从ADAS转向自动驾驶;三是如何实现节能减排。如何突破行业技术创新,成为汽车工程师最为关注的热点话题。

本次汽车电子论坛邀请了多名汽车行业技术专家,一起探讨最新行业议题,为工程师提供最前沿技术解决方案和应用。

芯禾科技作为国内EDA行业的领军企业之一,将在此次大会上展示其在EDA软件、IPD和SiP解决方案方面的最新研发成果,包括高速设计信号完整性分析、射频IC设计、集成无源器件、系统级封装等多个解决方案。

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会议日程

活动详情,请点击这里了解

ICCAD 2017

Xpeedic to Exhibit at ICCAD 2017

Date: Nov.16-17, 2017
Location: Beijing, China
Booth#: 148-149

Xpeedic Technology, Inc. will exhibit at CSIA-ICCAD 2017 Annual Conference & Beijing IC Industry Innovation and Development Summit (ICCAD 2017) in Beijing on Nov.16-17, 2017.

ICCAD is a most important annual event for IC design industry in China. It creates a biggest platform for enterprises within China IC industry chain to exchange their expertise and to build up networks. This year, the theme is “Driven by Innovations, Lead the Development”. In this annual general meeting, the Integrated Circuit industry, especially the opportunities and challenges faced by the IC Design industry, will be discussed in details in order to enhance innovation capability and improve the comprehensive capability of Chinese Integrated Circuit industrial chain, thereby satisfying the market demands and boosting international competence.

At booth 148-149 ,Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

Dr. Wenliang Dai, co-founder, VP Engineering, will also present the leading design method “2.5D/3D Advanced Packaging Design for Artificial Intelligence Era” within IP and IC design forum on Nov.17.

For more details, please go to the conference official website:  http://www.cicmag.com/bbx/532285-532285.html

sip con

SiP Conference China

Date: Oct 19-20, 2017(Thur.-Fri.)
Place: HILTON SHENZHEN SHEKOU NANHAI, Shenzhen, China

SiP Conferences China 2017 is the first System-in-Package (SiP) conference in China fully dedicated to covering all aspects related to SiPs business and technology to meet current and future SiP challenges. The conference features inspiring sparkers from entire SiP supply and design chain from OEM, Fabless, IDM, OSAT, EMS, EDA, silicon foundries, equipment and material suppliers together to one place in Shenzhen, China.

The SiP Conferences China 2017 is the premier international event that brings the best in packaging, SiP manufacturing assembly and test, advanced SiP architectures and design mythologies, new materials solution to enhance SiP electrical, thermal and mechanical integrities.

Dr.Feng Ling, CEO of Xpeedic Technology will lead the ‘SiP Design and System Integration’session during the conference. Xpeedic team will also demonstrate its latest SiP, IPD and related EDA solutions and products then.

We look forward to meeting you there.

Detail agenda:


For more details, please click here.

台湾workshop

EDA Workshop

尊敬的工程師夥伴,
隨著芯禾科技EDA工具的使用者愈來愈廣,我們很榮幸的向大家推出《芯禾科技EDA Workshop》系列活動,以幫助大家更直接的掌握我們軟件的應用技巧和實戰攻略。
本期課程將以高速訊號設計者的角度,和大家一起探討25Gbps的高速系統設計挑戰和方法。随着乙太網路速率的不斷的提升,在高速系统中將會面臨到哪些關鍵因素的模擬和評估,怎樣優化高速設計中的過孔,焊盤,AC耦合電容,如何整體評估在時域或頻域上的通道品質,這些獨門絕技,我們傾囊相授。
課程將由芯禾科技資深技術支援Frankie及黃智宇講師領銜主講,歡迎有興趣的工程師報名參加。機會難得,歡迎大家報名和專家面對面交流!

培訓安排

  • 時間:2017年10月18日
  • 地點:臺北市忠孝東路三段1號 (億光大樓2樓/北科會議中心)

课程安排

  • 9:00~9:30 簽到
  • 9:30~9:45 培訓概覽
  • 9:45~10:45 系統設計中關鍵因素的模擬和評估
  • 11:00~12:00高速設計中過孔,焊盤,AC耦合電容的優化方法
  • 12:00~13:30 午餐
  • 13:30~14:30 高速設計中線纜及玻纖效應的建模分析
  • 14:45~15:30 通道品質在時域及頻域上的評估
  • 15:30~16:00 軟體現場演示

發送“姓名+公司名稱+職位+手機號碼”至郵箱marketing@xpeedic.com,馬上報名!

EPEPS 2017

EPEPS 2017

Date: Oct 15-18, 2017.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

More details to see http://www.epeps.org/

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2017smic

SMIC 2017 Technology Symposium(Shanghai/Beijing)

Time & Location

  • Wednesday, Sept 13, 2017 in Shanghai
  • Thursday, Oct 12,2017 in Beijing

Xpeedic Technology will be exhibiting at the SMIC 2017 Technology Symposium Shanghai and Beijing on Sept. 13 and Oct. 12, 2017.

Xpeedic Technology will demonstrate its latest development EDA solution and IP solution as one of the valuable partners then. The analog/mixed-signal IC software tools help IC engineers to shorten their design cycle at the latest advanced semiconductor nodes. The growing IP portfolio on IPD delivers the industry-leading combination of performance and integration to enable SiP for RF front end module designs. All these tools and solutions have been widely adopted by companies who make mobile and IoT devices, computing and network systems.

SMIC Symposium_1 SMIC Symposium_2

北京培训会

Training Program

尊敬的工程师伙伴,

随着芯禾科技EDA工具的使用群体越来越广,我们很高兴的向大家推出《芯禾科技EDA培训系列课程》,以帮助大家更直接的掌握我们软件的应用技巧和实战攻略。本期课程将围绕高速数字设计,和大家一起探讨“5G时代下的高速系统设计挑战和方法”。随着无线技术的不断升级,高速系统中面临哪些关键因素的仿真和评估,怎样优化高速设计中的过孔、焊盘、AC耦合电容,怎样实现多板级联下数据通道的全覆盖评估,这些独门绝技,我们倾囊相授。
课程将由芯禾科技资深技术支持赵晨星、王锐和刘岩讲师领衔主讲。
本课程对购买了芯禾科技EDA工具的客户免费开放(每个License限报名两人),也欢迎其他有兴趣的工程师报名参加。
机会难得,欢迎大家报名和专家面对面交流!

苏州芯禾电子科技有限公司

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时间:2017年8月31日 周四 9:00-15:30
地点:北京红杉假日酒店 红桐厅 海淀区中关村双清路 89 号 A 座
培训费用:人民币1,000元,包括午餐、茶歇、配套软件及讲义等费用
报名优惠:前十名报名成功的工程师,减免所有培训费用
培训联系人:Max Cang (wei.cang@xpeedic.com)
课程安排:

9:00~9:30 签到
9:30~9:45 培训概览
9:45~10:45 系统设计中关键因素的仿真和评估
11:00~12:00 高速设计中过孔,焊盘,AC耦合电容的优化方法介绍
12:00~13:30 午餐
13:30~14:30 多板级联下数据通道的全覆盖评估
14:30~15:30 现场演示

点击这里,在线报名!