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Gary Smith EDA Names Xpeedic as “What to See @ DAC” Company

Austin, TX, June 21, 2017 – Xpeedic Technology Inc. was chosen by Gary Smith EDA as a What to See at DAC company at the 54th Design Automation Conference.

https://www.garysmitheda.com/wp-content/uploads/2017/06/What2SeeDAC2017.pdf

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Who:

Xpeedic is a global leading provider of EDA software, Integrated Passive Device (IPD), and System-in-Package (SiP) design solution. The analog/mixed-signal IC software tools help IC engineers to shorten their design cycle at the latest advanced semiconductor nodes. The signal integrity software tools enable faster design closure for IC package and PCB system designs. The growing IP portfolio on IPD delivers the industry-leading combination of performance and integration to enable SiP for RF front end module designs. All these tools and solutions have been widely adopted by companies who make mobile and IoT devices, computing and network systems.

What:

Xpeedic RFIC solution is Xpeedic’s flagship product tailored to RFIC applications, which  includes RFIC passive extraction tool IRIS, fast PDK model generation tool iModeler and RF passive PDK verification tool iVerifier.

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  • IRIS 2017 provides a 3D fast EM simulation tool integrated in Cadence Virtuoso design flow. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation. This design flow will greatly help RF IC designers to reduce the design cycles and achieve first-pass silicon success.
  • IRIS Plus is based on the industry leading acceleration technology for multilayer structures,and enables fast and accurate 3D EM simulation of passive devices and interconnects for RF/microwave ICs, modules, packages, and circuit boards in Windows environment; fully supports 2.5D interposer SI and PI simulation flow.

When/Where:

Design Automation Conference (DAC), Austin, US, June 18-22, Xpeedic Booth #1923.

Channel

EDA Release – ChannelExpert 2017

Xpeedic released the industry-leading high speed channel exploration tool —— ChannelExpert 2017 within its high speed signal integrity EDA solution this month.

ChannelExpert 2017 provides a full channel extraction and simulation solution based on dual engines in frequency domain and time domain. The latest update supports IEEE specs compliance mask, calculation of Channel Operation Margin (COM) and crosstalk, NRZ evaluation, and PAM4 eye-diagram check.

What’s new in ChannelExpert 2017

  • Implementation of Ribbon UI with the modern look and feel  as Microsoft Office products.
  • Built-in leading edge S-parameter based fast circuit solver to support latest IBIS and AMI model, even the next generation modulation PAM-4.
  • Support statistical eye diagram analysis with IBIS AMI model, designers can accurately simulate bit error rate measurements in a single simulation and display bathtub plots in what used to require a million transient simulations to attain the same coverage.
  • Accurate modeling of SERDES pre-emphasis and equalizers for AMI model with both NRZ and PAM-4 modulation, also provide GUI interface to modify equalizer parameters.
  • Support the latest version of input/output/IO IBIS model for SI simulation, and provide IBIS setting window for user to configure PKG parameters, model and other parameters.
  • Support BP channel quick creation and fast parametric sweep with built-in WYSIWYG slot number flow.
  • Support multiple LC and FC boards interconnect with backplane by pin mapping for BP template flow.
  • Full channel crosstalk analysis automation with only one click, including NEXT, FEXT, ICN, ILD, ICR, TDR and so on.
  • Powerful parallelized COM calculation to qualify a channel in the context of built-in specification, including 100GBASE-CR4, 100GBASE-KP4, 100GBASE-KR4, CAUI-4_C2C and so on.
  • Tabular COM values display and 2D CTLE, PDF, ISI, Jitter and ICR plotting help user get intuitive understanding of high speed channel performance.
  • Support both unencrypted and encrypted HSPICE subcircuit transient analysis with fast simulation speed.
  • Support several independent excitation sources, such as pattern source, PRBS, pulse, PWL and DC voltage.
  • Code-level integration of SnpExpert S-parameter plotting feature to improve ChannelExpert usability and dependency.
  • Seamlessly integrate ViaExpert model into ChannelExpert, and improve Xpeedic high speed tools’ interaction.
  • Add several built-in components to full cover high speed channel analysis, including single-ended and differential eye probe, TX/RX AMI, R/L/C lumped elements and so on.
  • Easy differential pair and crosstalk victim/aggressor setup.
  • Support multiple pins connected directly to the same port.

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please visit www.xpeedic.com to enjoy more fancy features from ChannelExpert 2017.

IRIS

EDA Release – IRIS 2017

We are glad to announce that Xpeedic released the fast EM simulation tool —— IRIS 2017 within its RFIC design solution this month.

IRIS 2017 provides a 3D fast EM simulation tool integrated in Cadence Virtuoso design flow. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation. This design flow will greatly help RF IC designers to reduce the design cycles and achieve first-pass silicon success.

What’s new in IRIS 2017

  • Export equivalent circuit for inductor, MiM capacitor, MoM capacitor and transformer in both HSPICE or Spectre sub-circuit format based on GA optimization algorithm.
  • Support multi-threading of matrix solving for cases with multiple ports to improve solving speedup and efficiency.
  • Improve via merge efficiency in mesher with 2x speedup.
  • Support mesh of MiM capacitor consists of multiple metal layers connected together.
  • Support layer-by-layer via merge before create iCell to improve simulation efficiency.
  • Support layer-by-layer duplicate metal pattern removal before create iCell for more advanced technology node.
  • Support via layer with the same name across multiple metal layers when define technology file.
  • Support Virtuoso 5.1, Virtuoso 6.1 and Virtuoso ICADV 12.2.
  • Add IRIS plugin in ADS simulation environment for RFIC, MMIC and LTCC customers, and run IRIS mesher and MoM solver in ADS directly based on ADS simulation options.
  • Import Calibre and ADS technology file to Xpeedic Technology, and convert to IRIS technology file automatically.
  • Add IRIS port automatically based on pin name in Virtuoso Layout L, Layout XL or more advanced version.
  • Using additional thread to invoke mesher, and avoid block Virtuoso main window to improve IRIS usability.
  • Auto decide sheet, thick and 3D metal model for MoM solver based on metal thickness, width and spacing.
  • Display mesh element number in mesh view window.
  • Upgrade SnpExpert to 2017.01 release with lots of new features and also modern Ribbon UI look and feel.

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please visit www.xpeedic.com to enjoy more fancy features from IRIS 2017.

Snp

EDA Release – SnpExpert 2017

Xpeedic released the industry-leading s-parameter exploration tool —— SnpExpert 2017 within its high speed signal integrity EDA solution this month.

SnpExpert 2017 provides a quick way to understand the electrical characteristics of the passive interconnectors in a system by not only viewing the S-parameter in frequency domain but also examining the time domain reflectometry(TDR) . It is a complete s-parameter post-processing solution, including gating, de-embedding, TDR/TDT, PAM4 eye diagram, Dk/Df extraction, s-parameter cascading.

What’s new in SnpExpert 2017

  • Support PAM-4 eye diagram, also add CTLE, FFE and FIR for Tx or Rx during eye diagram calculation.
  • For optimization based Dk and Df extraction flow, support dk, df and surface roughness as optimization targets, also support microstrip, stripline and CPW as built-in transmission line.
  • Implementation of Ribbon UI with the modern look and feel  as Microsoft Office products.
  • Support asymmetric TOD w/ and w/o fixture A or fixture B.
  • Support batch TOD calculation.
  • Support S-parameter cascading based on port connection relations.
  • Support single-ended crosstalk analysis in addition to differential pairs.
  • Support multiple S-parameter file average function to ensure both single-ended and differential data accuracy, and remove unwanted frequency points.
  • Add unwrap and moving_average functions to unwrap phase and calculate group delay.
  • Export detail TDT matrix between each victim and aggressor.
  • Explicitly output PASS/FAIL information for “Template Plot” based on compliance limit.
  • Add IL_fitted, ILD_rms and ICR_fit for template plot.
  • Update transformer L/Q/K/M calculation formula to accommodate both sequence and odd-even port type.
  • Add S-parameter and TDR quick plot panel in SnpExpert main window.
  • Enhance legend table to make it resizable

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please visit www.xpeedic.com to enjoy more fancy features from SnpExpert 2017.

IRIS Plus

EDA Release – IRIS Plus 2017

We are excited to announce that Xpeedic released a new flagship product —— IRIS Plus 2017 for RFIC, Module, and PCB designs with option to simulate 2.5D interposer with TSV for SI and PI.

Based on the industry leading acceleration technology for multilayer structures, IRIS Plus 2017 enables fast and accurate 3D EM simulation of passive devices and interconnects for RF/microwave ICs, modules, packages, and circuit boards in Windows environment; fully supports 2.5D interposer SI and PI simulation flow.

What’s new in IRIS Plus 2017

  • Implementation of Ribbon UI with the modern look and feel  as Microsoft Office products.
  • Support multi-threading of matrix solving for cases with multiple ports to improve solving speedup and efficiency.
  • Improve via merge and via array defeaturing efficiency in mesher with 2x speedup.
  • EM-friendly GDS layout importing and 3D layout building up.
  • Support importing net information of gds files.
  • Support identify nets of models, and create new SI/PI models based on selected nets.
  • Optimized group bump port adding flow, automatically identify net information of bump ports.
  • Support parametric and optimization sweep simulation for RFIC template and RFPCB template.
  • 3D CAD model view and net highlight feature provides direct visual check of the model.
  • Integrate SnpExpert to provide powerful S-parameter post-processing capability.
  • Add IRIS Plus plugin in ADS simulation environment for RFIC, MMIC and LTCC customers, and export ADS project to IRIS Plus directly.
  • Export IRIS Plus simulation project to HFSS for easy verification.
  • Support SI and PI simulation flow  for 2.5D interposer with TSV.
  • Powerful accelerated full-wave MoM solver integrated to solve large-scale interposer SI/PI problems.
  • Support via reduction for 2.5D interposer SI/PI simulation to improve simulation efficiency.

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please visit www.xpeedic.com to enjoy more fancy features from IRIS Plus 2017.

Via

EDA Release – ViaExpert 2017

ViaExpert 2017 with the latest FEM3D and Hybrid solver upgrade greatly improves the via simulation speed and accuracy. It allows designers at the pre-layout stage to quickly build via model and check the key signal integrity metrics such as insertion loss, return loss, and crosstalk. At the same time, post-layout simulation of vias and trace breakout is also enabled. The built-in connector footprint and stackup databases provide another convenient way of via modeling and simulation.

What’s new in ViaExpert 2017

  • Implementation of Ribbon UI with the modern look and feel  as Microsoft Office products.
  • Improve FEM3D simulation accuracy based on golden data correlation without sacrifice performance.
  • Support “Speed” and “Accuracy” mesh strategy to improve simulation efficiency based on user scenario.
  • Support trapezoidal trace for SMD template and AC Cap template.
  • Split one single via across multiple layers into three vias across the same layers, ut fanout to different position based on trace width and offset setting in footprint window.
  • Add lumped edge port, lumped internal port and coax port for signal pad in SMD template.
  • Support signal trace routing in top layer directly without via transition in SMD template.
  • Support mirror antipad extraction from “Create model from layout” flow.
  • Export ViaExpert simulation model to CST, and convert ViaExpert port to discrete face port and wave port in CST.
  • Support both combined antipad and uncombined antipad for AC Cap template.
  • Provide interface for user to define power/ground net name pattern, and import power/ground net to ViaExpert by default.

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please visit www.xpeedic.com to enjoy more fancy features from ViaExpert 2017.