EPEPS 2017

EPEPS 2017

Date: Oct 15-18, 2017.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

More details to see http://www.epeps.org/



SMIC 2017 Technology Symposium(Shanghai/Beijing)

Time & Location

  • Wednesday, Sept 13, 2017 in Shanghai
  • Thursday, Oct 12,2017 in Beijing

Xpeedic Technology will be exhibiting at the SMIC 2017 Technology Symposium Shanghai and Beijing on Sept. 13 and Oct. 12, 2017.

Xpeedic Technology will demonstrate its latest development EDA solution and IP solution as one of the valuable partners then. The analog/mixed-signal IC software tools help IC engineers to shorten their design cycle at the latest advanced semiconductor nodes. The growing IP portfolio on IPD delivers the industry-leading combination of performance and integration to enable SiP for RF front end module designs. All these tools and solutions have been widely adopted by companies who make mobile and IoT devices, computing and network systems.

SMIC Symposium_1 SMIC Symposium_2


Training Program





时间:2017年8月31日 周四 9:00-15:30
地点:北京红杉假日酒店 红桐厅 海淀区中关村双清路 89 号 A 座
培训联系人:Max Cang (wei.cang@xpeedic.com)

9:00~9:30 签到
9:30~9:45 培训概览
9:45~10:45 系统设计中关键因素的仿真和评估
11:00~12:00 高速设计中过孔,焊盘,AC耦合电容的优化方法介绍
12:00~13:30 午餐
13:30~14:30 多板级联下数据通道的全覆盖评估
14:30~15:30 现场演示