EPEPS 2017

EPEPS 2017

Date: Oct 15-18, 2017.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

More details to see http://www.epeps.org/

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2017smic

SMIC 2017 Technology Symposium(Shanghai/Beijing)

Time & Location

  • Wednesday, Sept 13, 2017 in Shanghai
  • Thursday, Oct 12,2017 in Beijing

Xpeedic Technology will be exhibiting at the SMIC 2017 Technology Symposium Shanghai and Beijing on Sept. 13 and Oct. 12, 2017.

Xpeedic Technology will demonstrate its latest development EDA solution and IP solution as one of the valuable partners then. The analog/mixed-signal IC software tools help IC engineers to shorten their design cycle at the latest advanced semiconductor nodes. The growing IP portfolio on IPD delivers the industry-leading combination of performance and integration to enable SiP for RF front end module designs. All these tools and solutions have been widely adopted by companies who make mobile and IoT devices, computing and network systems.

SMIC Symposium_1 SMIC Symposium_2

北京培训会

Training Program

尊敬的工程师伙伴,

随着芯禾科技EDA工具的使用群体越来越广,我们很高兴的向大家推出《芯禾科技EDA培训系列课程》,以帮助大家更直接的掌握我们软件的应用技巧和实战攻略。本期课程将围绕高速数字设计,和大家一起探讨“5G时代下的高速系统设计挑战和方法”。随着无线技术的不断升级,高速系统中面临哪些关键因素的仿真和评估,怎样优化高速设计中的过孔、焊盘、AC耦合电容,怎样实现多板级联下数据通道的全覆盖评估,这些独门绝技,我们倾囊相授。
课程将由芯禾科技资深技术支持赵晨星、王锐和刘岩讲师领衔主讲。
本课程对购买了芯禾科技EDA工具的客户免费开放(每个License限报名两人),也欢迎其他有兴趣的工程师报名参加。
机会难得,欢迎大家报名和专家面对面交流!

苏州芯禾电子科技有限公司

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时间:2017年8月31日 周四 9:00-15:30
地点:北京红杉假日酒店 红桐厅 海淀区中关村双清路 89 号 A 座
培训费用:人民币1,000元,包括午餐、茶歇、配套软件及讲义等费用
报名优惠:前十名报名成功的工程师,减免所有培训费用
培训联系人:Max Cang (wei.cang@xpeedic.com)
课程安排:

9:00~9:30 签到
9:30~9:45 培训概览
9:45~10:45 系统设计中关键因素的仿真和评估
11:00~12:00 高速设计中过孔,焊盘,AC耦合电容的优化方法介绍
12:00~13:30 午餐
13:30~14:30 多板级联下数据通道的全覆盖评估
14:30~15:30 现场演示

点击这里,在线报名!