Xpeedic 2018_JobQueue

EDA Release – New Upgrade – JobQueue 2018

We are glad to announce that Xpeedic released the simulation job queue system —— JobQueue 2018 this month.

JobQueue 2018 is an industry-leading simulation job management platform with dynamic allocation of computing resource, validity checking, HPC/PBS, and real-time display of simulation results to improve tool usage.

What's new in JobQueue 2018

  • Support both local and distributed run when submit simulation job.
  • Supported to configure HFSS project validation checking rules, and supported setting with each queue.
  • Supported to display job stat information of queue.
  • Supported to configure memory limitation of node.
  • Supported to set priority of job.
  • Supported to delete completed job by system administrator.
  • Supported to set max job submitted by user.
  • Added abstract information of job on usable queue on submition page, and display queue loading by different color.
  • Try to submit HFSS job automatically if error occured on checking license.
  • Supported to display node resource of job.
  • Supported to submit single frequency HFSS project job.
  • Optimized job time information on list, add job simulation duration column.
  • Added job status for waiting for license after submited.
  • Added getting error message of simulation and display on error information page.
  • Supported queue number of job on none-cluster job system.
  • Supported to search job by node address.
  • Added operation system exception detecting and handling.
  • Added to detect simulation started out of system.
  • Added warning and comfirming if user try to leave page before submitted job.
  • Optimized rule of generating job data directory.
Xpeedic 2018_SnpExpert

EDA Release – New Upgrade – SnpExpert 2018

We are glad to announce that Xpeedic released the S-parameter Exploration —— SnpExpert 2018 this month.

SnpExpert 2018 is a widely-adopted S-parameter exploration tool. It integrates all the S-parameter post-processing functions, and supports Python automation, DFE/CTLE auto-optimization, and new addition of 56Gbps and COM compliance.

What's new in SnpExpert 2018

  • Support Python script to invoke most SnpExpert features, including S-parameter import, plot, add mark, TDR, TOD and so on.
  • Support CTLE and DFE adaptive optimization and manual tuning features when plot eye diagram, also provide real time equalization preview plot to ease the tuning process.
  • Add new built-in compliances for S-parameter exploration, including OIF CEI_56G_LR_PAM4, OIF CEI_28G_VSR, IEEE 802.3cd, SAS 3.0, IEEE 802.3bz and MIPI D-PHY compliances.
  • Support parallelized COM analysis for IEEE 802.3cd, IEEE 802.3bs and IEEE 802.3by based on the latest compliance requirements.
  • Add “Apply to Cable/TML” option in TOD and halve S-parameter to improve long transmission line de-embedding accuracy and speed.
  • Add Open-Thru De-embedding (OTD) method for on-chip de-embedding.
  • Support both “Simplified ” and “Advanced” S-parameter cascading to accommodate difference usage scenario.
  • Support multiple data curves gating with only one click, and export the whole S-parameter after gating.
  • Support FFT_Mag(), FFT_dB(), FFT_Imag() and FFT_Real() functions for time domain data sources.
  • Support PhaseDelay() and PhaseDelayDiff() to calculate group delay of both single-ended and differential S-parameter.
  • Support horizontal line when add markers to measure delay and skew value.
  • Explicit output PASS/FAIL information for “Channel” and “Template Plot” based on compliance limit.
  • Support global variable definition and recursive invoke to better reuse between different data sources.
  • Add S, Y, Z and RF template quick plot panel in SnpExpert main window.
  • Support both single-ended and differential NEXT/FEXT/THRU S-parameter export when split S-parameter file with large number of ports.
  • Support S-parameter plot with odd number of differential pairs.
  • Support opening SnpExpert project by double click.
  • Save project status and user settings when software encounter abnormal situation.

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Xpeedic 2018_ViaExpert

EDA Release – New Upgrade – ViaExpert 2018

We are glad to announce that Xpeedic released the 3D Via Modeling and Simulation —— ViaExpert 2018 this month.

ViaExpert2018 is an industry-leading via modeling and simulation tool. It supports remote and distributed simulation that are managed by Xpeedic Distributed Processing Management(XDPM), manual wiring, and Keepout parameterized library and CMF/SMP modules to provide better solutions for design optimization of 56Gbps and higher speed system.

What's new in ViaExpert 2018

  • Support HPC, remote and local simulation under the management of XDPM (Xpeedic Distributed Processing Management) module to maximize high computing machine availability.
  • Unify simulation jobs submit and status monitor flow in “Submit Job” and “Job Manager” to support more user-friendly and real-time feedback batch run.
  • Support arbitrary parameterized keepout definition, management and usage in 2D footprint window to explore the optimal antipad geometry. The keepout shape can be defined by the unite of lines/arcs or regular parameterized geometries.
  • Adjust 2D footprint window features to “Footprint” page and categorized as “Via”, “Trace”, “Port” , “Keepout” and “Component” to give user intuitive and convenient operation links.
  • Support single-ended and differential manual routing with obstacle avoidance capability.
  • Support arbitrary via array define, move, duplicate, align top/bottom/left/right, distribute horizontally/vertically, undo and redo features in 2D footprint window.
    Add CMF and SMP template to quick build and explore capacitor and SMP performance.
  • Support the RLC boundary to add RLC circuits in serials or in parallel, also mark RLC boundary position for both 2D/3D view if added.
  • Add “Material Library” module to unify frequency dependent material define, modify, export and re-use flow across different projects, and even different teams. 
    Support showing or hiding metal layers in the 2D footprint window.
  • Support parametric of layer thickness, trace width with multiple segments for both template and layout flow and combined anti-pad, also export parameterized parameters to HFSS.
  • Code-level integration of SnpExpert basic S-parameter and TDR plot features to give user more user-friendly flow to explore simulation results.
  • Support easy and efficient Allegro to ViaExpert plugins, export allegro layout to ViaExpert with only one-click based on net selection.
  • Support opening ViaExpert project by double click.
  • Automatically save ViaExpert project status and user settings at user defined interval.

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Xpeedic 2018_iModeler

EDA Release – New Upgrade – iModeler 2018

We are glad to announce that Xpeedic released the passive PDK Model Generation —— iModeler 2018 this month.

iModeler 2018 provides RFIC designers a fast solution for RF passive design in Cadence Virtuoso platform. The solution employs a full-wave 3D EM solver with both multi-core and distributed parallelization feature that greatly reduces the EM simulation time. It includes several types of tools for modeling and parameter extraction which can deal with most cases. This software will make RF passive device design easier and increase the efficiency.

What's new in iModeler 2018

  • Support bias table and rho table in iModeler to account for technology variations for advanced IC nodes.
  • Support PCell synthesis database buildup based on Artificial Neural Network (ANN) algorithm for PDKtoModel flow.
  • Add interleave transformer and splayed inductor templates to quick create PCell and parameterized equivalent circuit.
  • Support create PCell only flow without run EM simulation.
  • Support Equivalent Circuit generation for each new iCell generated from sweep table.
  • Add “Abort All” button to stop iModeler batch EM simulation defined in sweep table.
  • Reduce iModeler simulation options to simplify IRIS usage and give better user experience.
Xpeedic 2018_IRIS

EDA Release – New Upgrade – IRIS 2018

We are glad to announce that Xpeedic released the RFIC Passive Extraction —— IRIS 2018 this month.

IRIS 2018 obtained the GF 22FDX process certification, provides a 3D fast EM simulation tool integrated in Cadence Virtuoso design flow. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation.

 What's new in IRIS 2018

  • Support bias table and rho table in IRIS to account for technology variations for advanced IC nodes. 
  • Improve via merge efficiency with 10x speedup for large scale via arrays and make via merge one-time operation to save re-run overhead.
  • Support IRIS export to HFSS 3D Layout with tuned simulation settings to ensure accuracy as part of Xpeedic and Ansys software partnership.
  • Unify IRIS2HFSS and IRIS2HFSS3DLayout flow to simplify IRIS simulation project export usage.
  • Support automated port search and define feature based on pre-defined pin position.
  • Support Synopsys StarRC Interconnect Technology Format (*.itf) and IRIS Technology (*.lyr) conversion.
  • Reduce IRIS simulation options to simplify IRIS usage and give better user experience.

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Xpeedic 2018_Hermes

EDA Release – New Product – Hermes 2018

We are glad to announce that Xpeedic released the package and system SI analysis —— Hermes 2018 this month.

Hermes2018 is a co-simulation platform for chip, packaging and PCB, and based on the leading FEM3D and Hybrid simulation engine technology. It introduces two efficient simulation processes (Hermes SI and Hermes RF) for high speed and RF applications in this release, which not only satisfies the fast simulation requirements for high-speed SerDes and DDR on the packaging and board level, but also meets the RF/digital hybrid simulation requirements, prompting the evolution of advanced packaging and high-speed signal simulation technology.

What's hot in Hermes 2018

  • Support net based signal integrity analysis flow to quick create package and PCB simulation project, and explore high speed SerDes, DDR and RF/Digital mixed SI issues in Hermes SI and Hermes RF flow.
  • Built-in fast 3D FEM solver and leading edge hybrid solver offers better capacity and speed compared to other tools in market.
  • Optimized tetrahedron mesh improves simulation speed and precision, also provides “Speed” and “Accuracy” mesh strategy to improve simulation efficiency without sacrifice accuracy based on user scenario.
  • Support multiple layout formats import, including *.brd, *.sip, *.mcm, ODB++ and *.vsf.
  • Support Adaptive frequency sweep and multi-threading processing technology to achieve excellent performance speedup.
  • Support “Rect”, “Poly” and “Auto” simulation model cut methods to give user flexible select of SI critical areas.
  • Support several port excitation to meet different usage scenario, including lumped port, coax port, wave port, ring port and RLC boundary.
  • 3D-View makes the model check easier.
  • Integrate SnpExpert into Hermes to automate S-parameter and TDR plot.
  • Easy export Hermes simulation project to HFSS for easy verification.

封装

Xpeedic 2018

Xpeedic released new EDA 2018 suites

We are excited to announce the release of Xpeedic 2018 EDA software.

In this release, Xpeedic introduces new product Hermes, many new features and enhancements, and most importantly the memory usage of FEM3D dropped 60% without sacrificing computing efficiency. The new release includes all the three product lines: IC design, high speed signal integrity, and high-performance web solution, which further strengthens Xpeedic’s EDA product proposition: fast, accurate and user friendly.

Highlights in EDA 2018.01

New Product – Hermes

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Hermes2018 is a co-simulation platform for chip, packaging and PCB, and based on the leading FEM3D and Hybrid simulation engine technology. It introduces two efficient simulation processes (Hermes SI and Hermes RF) for high speed and RF applications in this release, which not only satisfies the fast simulation requirements for high-speed SerDes and DDR on the packaging and board level, but also meets the RF/digital hybrid simulation requirements, prompting the evolution of advanced packaging and high-speed signal simulation technology. 

IRIS/iModeler New Feature

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IRIS2018 supports the bias table and rho table for advanced technology node, and takes consideration the conductivity and actual metal line width change within different technology. IRIS obtained the GF 22FDX process certification. It supports the auto-addition of the pin, and the efficiency of via defeaturing is increased by 10x.

ViaExpert New Feature

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ViaExpert2018 is an industry-leading via modeling and simulation tool. It supports remote and distributed simulation that are managed by Xpeedic Distributed Processing Management(XDPM), manual wiring, and Keepout parameterized library and CMF/SMP modules to provide better solutions for design optimization of 56Gbps and higher speed system.


ChannelExpert New Feature

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ChannelExpert 2018 is an unique tool for full channel extraction and simulation. It supports automatically extract the crosstalk between multiple boards and multiple channels; supports developed frequency domain and statistical eye diagram simulation to realize full-channel simulation, crosstalk, COM analysis and statistical eye diagram analysis. 

SnpExpert New Feature

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SnpExpert2018 is a widely-adopted S-parameter exploration tool. It integrates all the S-parameter post-processing functions, and supports Python automation, DFE/CTLE auto-optimization, and new addition of 56Gbps and COM compliance.

JobQueue New Feature

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JobQueue2018 is an industry-leading simulation job management platform with dynamic allocation of computing resource, validity checking, HPC/PBS, and real-time display of simulation results to improve tool usage.

In addition, Xpeedic also releases a complete simulation process for IC design in advanced technology node with the partnership of Ansys HFSS, and XpeedicBridge, an interface module to connect most of the mainstream EDA tools with Xpeedic.

IMS2018-1

Xpeedic to Exhibit at IMS2018 in Philadelphia

Xpeedic Technology will showcase its latest solutions at the 2018 IEEE MTT-S International Microwave Symposium (IMS) in Philadelphia, June 12-14.

Featured as in-booth demos will include

  • Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced Process Nodes.
    This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.
  • Integrating IRIS Plus in Nuhertz FilterSolutions to Enable Fast Filter Simulation.
    It presents a fast filter design flow by taking advantage of both the filter synthesis from Nuhertz FilterSolutions and the 3D full-wave electromagnetic simulation from Xpeedic IRIS Plus. Designers can use this combined single flow for fast filter prototyping without manually transferring CAD data from layout to EM simulation, thus improving the design efficiency.
  • Through Glass Via (TGV) Based Integrated Passive Device Technology for RF Front End Design
    Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. Xpeedic will introduce passive device (such as filters and diplexers) technology built with TGV, which can have less in-band insertion loss and greater out-of-band rejection yet still compact size.

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For more information, visit Xpeedic at Booth 1705 at the show.

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DAC2018

Xpeedic to Exhibit at DAC2018

Date: June 25-27, 2018

Place: San Francisco, CA, US

Booth#: 2041

The Design Automation Conference (DAC) is the premier conference devoted to the design and automation of electronic systems (EDA), embedded systems and software (ESS), and intellectual property (IP).

As a global leading provider of EDA software and Integrated Passive Device (IPD), Xpeedic will showcase its EDA and IP solution and several fascinating demos, including IRIS for passive modeling and simulation in advanced nodes, IRIS for both high-resistivity silicon (HRSi) and through-glass-via (TGV) based IPD design, Hermes for 3D package simulation, and expert-series signal integrity tools for high speed systems.

wechat-demo

Xpeedic is also invited to participate at Samsung Foundry's DAC 2018 Theater as a valuable SAFE partner. Xpeedic CEO, Dr. Feng Ling will give the presentation titled “Accurate Passive Modeling and Simulation for Advanced Process Nodes” at Samsung's booth.

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More details to see https://dac.com/