EPEPS 2018

Xpeedic Tutorial at EPEPS 2018

Date: Oct 14-17, 2018.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Dr. Feng Ling, CEO of Xpeedic Technology, will lead Tutorial II: EM solver technologies from chip to system: challenges and opportunities at EPEPS Sunday Tutorials.

epeps tutorials

At the same time, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

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More details to see http://www.epeps.org/

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CableExpert: Fast and Accurate Cable Modeling and Simulation

Cable assembly is a key component in network systems. Accurate modeling of cables is becoming a necessity to achieve the desired signal integrity with multi-gigabit data rate. Twinaxial cable used for SFP and QSFP interface in 10G/40G/100G Ethernet is such an example. Many parameters have significant impact on signal quality such as drain type and shielding pattern, to name a few. Engineers need a fast and accurate way to model and simulate the cable with high confidence in signal integrity.

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Xpeedic to Present at Japan SOI Design Workshop

Date: 25 October 2018

Place: Yokohama, Japan

The SOI Industry Consortium organizes for the 4th time its annual workshop in Japan. During the two day workshop, leading companies working with SOI technologies will meet in Yokohama to discuss about designing with FD & RF SOI technologies and in Tokyo to exchange on more than Moore, with special focus on silicon photonics, MEMS & sensors, and the SOI manufacturing ecosystem.
Xpeedic is an active SOI Industry Consortium member these years. Xpeedic’s passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic’s IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In Yokohama workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will present at EDA/IP II session (2:30pm, Thursday, 25 October 2018) together with other leading EDA vendors, such as Synopsys, Cadence, Silvaco, to discuss RF-SOI for RFFE Solution from EDA perspective.

Click here for more details.

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IRIS Plus: Fast RFIC and MMIC Passive Extraction simulation tool

Xpeedic IRIS Plus provides a 3D EM simulation tool of passive devices and interconnect structures for RF/microwave chips, modules, packages, and circuit boards. Industry leading multi-layer structure of the method of acceleration technology, fast and accurate simulation of complex electromagnetic effects, including the skin effect of the conductor, proximity effect and multiple dielectric loss. IRIS Plus support multi-thread calculation, its solver greatly reduce the EM simulation time, improve the design efficiency. IRIS Plus support import IRIS project file, GDS, DXF file, also integrate RFIC template modeling, and RFPCB template modeling. The IRIS Plus design flow will greatly reduce the IC design time of RFIC designer.

 Please click the link below to download the file.

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Hermes: High Speed PCB Signal Integrity Analysis

Impedance discontinuity in the signal path has a significant impact on signal integrity for high speed channel design. Among the many discontinuities, via discontinuity plays an important role in the high speed channel design. Three-dimensional full-wave EM simulation is constantly used to analyze via discontinuity, but there are many defects in the traditional 3D full-wave simulation, for example, the model creation is complex and time-consuming. Hermes provides a fast and accurate way to simulate PCB board and package structure of signal integrity problems, such as insertion loss, return loss, crosstalk, etc., also allows the designer to simulate and track processing for post-layout. Hybrid algorithm have a very fast speed in the premise of ensuring the accuracy of the results, which greatly improve the efficiency of the simulation. The powerful parametric sweeping function can be made by changing the properties of the pad, the stackup, the trace layer and the depth of the back hole, and the results can be easily compared with others. By using the unique electromagnetic field simulation engine, the S parameters can be extracted efficiently and accurately, and update the physical parameters such as the length, width, distance, and stackup to optimize the design. Hermes also provides the feature of exporting to HFSS, which can be used to quickly create models.

Please click the link below to download the file.

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ChannelExpert: High Speed Channel Exploration

High speed serial channel design is becoming more and more challenging because of the ever increasing data rate. At multi-gigabit per second data rate, channel designers must characterize all the pieces in the signal path from transmit to receiver including connector, via, and trace, which are typically represented by either IBIS model, AMI model, S-parameter blocks or RLGC transmission line (TML) model. Conventional SPICE-like circuit simulator has difficulty to efficiently handle the channel with mixed S-parameter and TML models, especially with large number of ports. ChannelExpert provides a fast and accurate way to address the signal integrity issue arising from the cascaded network of S-parameter blocks and TML models. Its frequency domain cascading technology and 2D RLGC full wave transmission line solver enable quick and accurate channel simulation. Its intuitive graphic interface lets you easily design, analyze and optimize your high speed serial links for compliance with design standards. Its quick channel build by table allows easy channel setup. Its parametric support enables the quick what-if analysis by sweeping the different S-parameter models for the channel element of interest. S-parameter based fast circuit solver supports the latest IBIS and AMI model, and provides the next generation modulation PAM-4 analysis flow.

Please click the link below to download the file.

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SnpExpert: S-Parameter Exploration

S-parameters, traditionally used in RF/Microwave design, are widely adopted by high speed digital designs as the multi-gigabit interface continues to advance to higher data rate. Xpeedic SnpExpert provides a quick way to understand the electrical characteristics of the passive interconnectors in a system by not only viewing the S-parameter in frequency domain but also examining the time domain reflectometry (TDR). One-click definition of differential pairs and victim/aggressor setup, together with the built-in NEXT, FEXT, PSXT, ILD, ICR, and ICN, allows user to quickly evaluate the crosstalk. The built-in delay and skew calculator requires no cumbersome circuit schematic setup. The built-in compliance metrics with IEEE 802.3ap, 802.3ba, 802.3bj, SAS, PCIe, SATA and OIF CEI 25G/28G standards quickly reveal the S-parameter compliance. The built-in passivity, causality, reciprocity, and stability metrics tell the quality of the S-parameter, and built-in enforcement algorithm fix S-parameter quality issues. The built-in template automates the process from S-parameter plotting to report in Word or PPT. The through-only de-embedding method helps SI engineers to quickly obtain the DUT characteristics by removing the fixture effect. Accurate NRZ and PAM-4 eye diagram calculation with equalization and pre-emphasis technology help user get an intuition feeling about high speed channel performance.

Please click the link below to download the file.

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Integrating IRIS Plus in Nuhertz FilterSolutions to Enable Fast Filter Design

This application note presents a fast filter design flow by taking advantage of both the filter synthesis from Nuhertz FilterSolutions and the 3D full-wave electromagnetic simulation from Xpeedic IRIS Plus. The combined flow offers designers a single flow for fast filter prototyping without manually transferring CAD data from layout to EM simulation, thus improving the design efficiency.

Introduction

Radio-frequency (RF)/microwave filter is an important component in a high-frequency system. Designing such a filter for given performance specifications is often a tedious and iterative process.

Nuhertz FilterSolutions provides a quick and accurate approach for filter synthesis and analysis. It supports various filter topologies including distributed filters built on microstrip, stripline, or suspended substrate. However, the high frequency characteristics such as parasitic effect are not considered. Adding Xpeedic IRIS Plus, a 3D full-wave electromagnetic solver, into the flow can address this problem.

It is the purpose of this application note to demonstrate the advantages of combining circuit-based synthesis with EM-based simulation in RF/microwave filter design. Figure 1 shows the combined Nuhertz-Xpeedic flow to enable fast filter prototyping.

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Figure 1 Diagram showing the combined Nuhertz-Xpeedic flow.

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Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced Process Nodes

This application note presents a combined IRIS-HFSS flow for passive modeling and verification in advanced process nodes, which gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage, but also the verification capability at the sign-off stage.

Introduction

Electromagnetic simulation of passives and interconnects becomes challenging for IC designers in advanced process nodes. First, an integrated environment is required in which EM simulation tool is seamlessly integrated within the design platform. Second, fast passive modeling and synthesis is needed at the design stage. Third, the very accurate three dimensional EM simulation is desired for sign-off or IC-package co-simulation.

In this application note, a combined IRIS-HFSS flow seamlessly integrated in Cadence Virtuoso platform is demonstrated, as shown in Figure 1. At the design stage, IRIS and iModeler enable fast passive modeling and synthesis with its accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique. At the verification stage, HFSS enables accurate 3D simulation and possible IC-package co-simulation.

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Figure 1 Combined IRIS-HFSS flow for IC designers.

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Through Glass Via (TGV) Based Integrated Passive Device Technology for RF Front End Design

This white paper presents a comprehensive study on TGV based integrated passive devices (IPD) in the context of comparing with other IPD technologies such as low-temperature-cofired-ceramics (LTCC), high resistivity silicon (HRSi), and glass substrate. The comparison is not only on the component (inductor) level but also on the system level, where a carrier aggregation diplexer is designed. Further TGV process improvement is also suggested based on the study.

Introducion

Mobile and IoT device market has experienced tremendous growth in the past. While Moore’s law continues to drive the technology to shrink for the digital portion of the devices, the RF portion does not scale in the same rate. The further reduction in cost and size comes from the passive integration. To meet the ever growing demand reduce size and cost, increase functionality, integrated passive device (IPD) technology has become a viable technology for RF front end designs. It has evolved from low-temperature cofired ceramics (LTCC) to thin-film technologies such as the one using high-resistivity silicon (HRSi) or glass substrate.

Recently, Through Glass Via (TGV) technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. Three-dimensional solenoid inductors can be constructed with TGVs for better quality-factor compared with 2D planar inductors. Glass’s lower dielectric constant and higher resistivity compared to silicon lead to better high frequency performance. Passive devices such as filters and diplexers built with TGV can have less in-band insertion loss and greater out-of-band rejection yet still compact size.

This white paper will demonstrate the TGV performance by comparing TGV inductor with those built on LTCC, HRSi, and glass substrate. The similar comparison is also carried out on system level. A carrier aggregation (CA) diplexer is designed with TGV, LTCC, HRSi and glass, respectively. Their performance such as IL, isolation, and attenuation is compared. Further improvement on TGV performance is studied from the TGV process perspective.

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