Combined IRIS-HFSS Flow for Passive Modeling and Verification in TowerJazz RF and HPA Nodes

This application note presents a combined IRIS-HFSS flow for passive modeling and verification in TowerJazz RF and HPA nodes, which gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage, but also the verification capability at the sign-off stage.

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Full Board

Fast Full Board Crosstalk Scan for Signal Integrity Sign-Off for High Speed PCB Designs

Abstract—Crosstalk analysis for high speed PCB design becomes more and more important due to the high data rate and tightly coupled routing. Traditional circuit-based analysis can not meet the accuracy demand. Three-dimensional (3D) full-wave electromagnetic solver is required to capture the complex 3D PCB environment and the frequency-dependent phenomena. However it is prohibitively expensive to simulate the practical large board cases and the resultant tabulated S-parameter cannot be directly used to quantify the crosstalk level. This paper introduces a novel hybrid solver techniques with improved speed and accuracy. The new crosstalk metrics to quantify the crosstalk level are also developed by post-processing S-parameter. Combining these two techniques allows designers to achieve full board crosstalk in a few hours as planned intended with using the tool, which significantly reduces the post-layout review time, allows layout optimization and ensures a timely sign-off.

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Foamed Cable

An Empirical Model for Foamed High-Speed Cable

Abstract—As the foaming technology becoming widely adopted for high-speed cable, the challenge of modeling the generic foaming which is a combination of skin and foam structure becomes critical for both cable design and channel analysis. An empirical model is proposed and validation with measurements are presented in this paper for targeted applications.

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IRIS: Fast EM Simulation with Virtuoso Integration

In high frequency silicon circuit design, passive devices, interconnect, and their mutual coupling have to be taken into account via electromagnetic (EM) simulation. Full-wave EM simulation is becoming necessary to cover the RF frequency of interest including multiple harmonics compared to quasi-static RC extraction. Cadence Virtuoso based schematic and layout flow is widely adopted for IC designers. However, lack of the built-in full-wave EM simulation tool leads to frequent transfer of the layout data between Virtuoso environment and outside EM tools, which is very manual and error-prone. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation. This design flow will greatly help IC designers to reduce the design cycles and achieve first-pass silicon success.

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ViaExpert: 3D Via Modeling and Simulation

Impedance discontinuity in the signal path has a significant impact on signal integrity for high speed channel design. Among the many discontinuities, via discontinuity is the critical one which requires extra attention in channel design. Three-dimensional full-wave EM simulation is constantly used to analyze via discontinuity. Conventional 3D full-wave simulation approach suffers from various drawbacks including the complex model creation and the long simulation time. ViaExpert provides a fast and accurate way to simulate via structures for both pre-layout and post-layout scenarios. For pre-layout analysis, various built-in templates allow users to quickly assemble the models, analyze and optimize SMA, SMD, AC Cap, via array and BGA physical parameters based on design constrains. The model can also be built by extracting the area of interest from the existing layout. The fast 3D FEM and hybrid solver yields accurate results with unprecedented speed. Optimal 3D mesh improves the simulation accuracy and speed. The powerful parameterization on the critical via variables such as antipad size, trace escape layer, and backdrill layer enables quick what-if analysis. Additional features such as exporting to HFSS and CST are also provided for quick benchmarking.

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JobQueue: Simulation Job Management Platform

JobQueue is a web based platform to submit, monitor and manage your simulation jobs, including IRIS, HFSS and so on. As a web application, JobQueue utilizes both client hardware devices and servers based on Client/Server mode, so it’s quite easy to deploy, and get your team to work across the region with only one deployment. JobQueue is quite easy to use, anyone with IE browsing experience can pick up soon. In JobQueue, all heavy computational simulation jobs will dispatch automatically to computing machines’ cluster in order to maximize hardware resource utilization, and make the best of parallel computing and distributed computing. JobQueue built-in queuing and batch simulation system help customer adjust task priority, manage computing resource, save GUI license and increase simulation tool’s utilization ratio. Project management module will supervise and manage submitted tasks for easy back trace and reuse, which greatly increase value to the business enterprise knowledge backlogs. Simulation results real time display forward to browser will definitely improve simulation productivity.

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TmlExpert: Tml Modeling and Simulation

TmlExpert is a fast and accurate Tml modeling and simulation tool.

Transmission lines are key building components which plays an important role in signal integrity. As data rate increases to high Gbps speed, accurate modeling of transmission lines including wideband dielectric model, conductor surface roughness, and solder mask layer is becoming necessity. Calculating impedance with 2D RLGC solver is commonly used for impedance control purpose. Given the length of the transmission line, the S-parameter, TDR, delay, and resultant eye-diagram with bit stream input are often needed. In high speed PCB layout, serpentine traces are often used to meet timing specification. Tabbed routing is newly proposed to improve the route channel utilization However, the signal integrity impact is required to be evaluated.

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