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Xpeedic to Exhibit at GTC 2019 – US

  • Date: September 24, 2019
  • Place: Santa Clara, CA, US

As a valuable GLOBALFOUNDRIES RFwave and FDXcelerator program partner, Xpeedic Technology will showcase its latest solutions at GTC US 2019 (GLOBALFOUNDRIES Technology Conference) in Santa Clara, CA, September 24, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in GF’s Advanced Nodes

As Morre’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by GLOBALFOUNDRIES FD-SOI 22FDX and FinFET 12LP Process widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (Silicon, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and serviceFin

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Xpeedic to Exhibit at SMIC 2019 Technology Symposium

  • Time: September 19, 2019
  • Location: Shanghai

Xpeedic Technology will be exhibiting at the SMIC 2019 Technology Symposium Shanghai on Sept. 19. Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in SMIC Advanced Nodes

As Moore’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

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Xpeedic to Exhibit at FD-SOI Forum and RF-SOI Workshop 2019

  • Date: September 16-17, 2019
  • Place: Shanghai, China

The 7th Shanghai FD-SOI Forum & 2019 International RF-SOI Workshop will be held in Shanghai at September 16-17, 2019.

The 7th Shanghai FD-SOI Forum

This 7th Shanghai FD-SOI Forum will focus on Automotive and IoT applications, products, and supply chain with AI/Edge Computing being discussed in conjunction with Automotive and IoT. There are keynote speeches by executives from Fabless and foundries. The theme of this year’s Forum is Deployment of FD-SOI, for which there are two sessions: AIoT using FD-SOI and automotive electronics using FD-SOI.

Visit here for FD-SOI event.

2019 International RF-SOI Workshop

The RF-SOI Workshop will be focused on 5G connectivity and its opportunity for SOI Industry. Keynote speaker will include 5G carrier, system provider and device maker. They will provide insight on the latest development on 5G deployment and RF-SOI readiness. In the afternoon session, there will be “China RF-SOI Ecosystem” and “RF Value Chain”. It will be focused on RF design and foundry platform for 5G RF-SOI application in China. Also worldwide SOI supply chain will be presented.

Visit here for RF-SOI event.

As an active member of SOI Industry Consortium, Xpeedic has been collaborating with members in the SOI eco-system to provide innovative EDA tools and IP solution to its customers. Xpeedic’s passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic’s IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In 2019 International RF-SOI Workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will give a presentation titled “Innovative EDA Solutions to Enable Differentiated RF-SOI Designs” in the China RF-SOI Ecosystem session to showcase Xpeedic’s contribution.

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SiP Conference China 2019

  • Date: Sept 10-11, 2019
  • Place: Shenzhen, China

SiP Conference China 2019 is the third System-in-Package (SiP) conference in China fully dedicated to covering all aspects related to SiPs business and technology to meet current and future SiP challenges. The conference features inspiring sparkers from entire SiP supply and design chain from OEM, Fabless, IDM, OSAT, EMS, EDA, silicon foundries, equipment and material suppliers together to one place in Shenzhen, China.

The arrival of 5G and Artificial intelligent (AI) technology is having a massive impact on wireless, IoT, autonomous and connected vehicles, automated smart cities, base stations, data storage, computing and networking. The conference and exhibition will highlight System in Package technologies that are helping to implement cost effective solutions of electronic components integration in small size SiP packaging. The program will include several keynote speakers and technical sessions, followed by a panel discussion of key issues, including SiP assembly and test, advancement in materials and substrates and system solutions for targeted market applications.

The conference will cover the following vital topics:

  • SiP Business and Technology Trends
  • SiP System Solutions for Smartphone and IoT
  • 5G NR & mmWave SiP Solutions
  • 2.5D/3D and WLSiP Applications, Assembly and Test Challenges
  • Advance Material & Substrate Solutions for SiP
  • provide dynamic learning and technology updates for SiP related trends

Dr.Feng Ling, CEO of Xpeedic Technology will lead the session during the conference. Dr. Wenliang Dai, co-founder, VP Engineering, will present “Enabling SiP Design with Differentiating Simulation Technologies” within SiP Design Challenges forum on Sept.11. Xpeedic team will also demonstrate its latest SiP, IPD and related EDA solutions and products then.

 For more details, please click here.  General chair

sip-nk  General Chair:Nozad Karim  VP, Product Line SiP, Amkor Technology

Nozad Karim presently is the Vice President of SiP & System Integration at Amkor Technology. He has over 20 years’ experience with SiP & module technology developments, and over 30 years of experience working with semiconductor packaging, circuit and system designs for digital, analog, and RF/Microwave applications. Prior to Amkor, he served in engineering and management roles with Motorola Communication, Texas Instruments, & Compaq Computer.

Technical chair

sip-dv  Techinical Chair:David Lu  VP, New Technology Research Institute vivo Mobile Communication Co., Ltd.

With over 25+ years experience in electronics process engineering, material science and technology strategic planning, David is leading innovative assembly technology development for high volume manufacturing operation of consumer electronics, including smartphones, smartwatches, SiP modules, automotive modules, tablets, PC, etc. David has spent many years on Design for Manufacturing (DFM), developed DFX design guidelines, wrote assembly process specifications & standards, established NPI (New Product Introduction) verification facilities and audited EMS outsourcing. Prior to Huawei, David also held a several senior and principal technical positions in Nokia Mobile Phones, Nortel Networks and Alcatel. David is also holding several technology patents in US, Europe and China, leading industrial consortium and external technology collaboration and actively providing keynote presentations and speeches in conferences, seminar and training courses with international background and East-meets-West culture & multi-language capabilities.

Technical chair

sip-rb  Technical Chair:Rozalia Beica  VP of Technology, IMAPS

Rozalia Beica is currently Global Director Strategic Marketing with DowDuPont. She is focusing on strategic activities, identifying new technologies and markets, growth opportunities across Electronics & Imaging Division. She has 25 years of international working experience across various industries, including industrial, electronics and semiconductors. For 18 years she was involved in the research, applications and strategic marketing of Advanced Packaging, with global leading responsibilities at specialty chemicals (Rohm and Haas), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining Dow, Rozalia was the CTO of Yole Developpement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing.

session leader

sip-fl  Session Leader: Feng Ling  CEO, Xpeedic Technology

Feng Ling (S’97-M’00-SM’07) is currently Founder and CEO of Xpeedic Technology, Inc., a leading EDA software and IP provider in chip-package-system solution. In 2000, he was a Senior Staff Engineer/Scientist at Motorola (now Freescale Semiconductor), working on RF module technology with LTCC and HDI substrate. In 2002, he joined Neolinear, where he led the electromagnetic solver development for mixed-signal RF integrated circuit designs. Through Cadence acquisition of Neolinear, he joined Cadence in 2004. As VP of Engineering, he co-founded Physware in 2007 (acquired by Mentor Graphics in 2014). In 2010, he founded Xpeedic Technology, Inc., continuing the efforts to bring the novel solution to the RF design and high speed digital community. Dr. Ling received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2000. He is a Senior Member of IEEE. He has authored and co-authored 2 book chapters and more than 60 papers in refereed journals and conference proceedings. He has served on the technical program committee of DesignCon, EDAPS, and EPTC. He has 5 US patents. He was the inaugural recipient of the Y. T. Lo Outstanding Research Award from the Department of Electrical and Computer Engineering at UIUC in 1999. He has been an Affiliate Associate Professor in the Department of Electrical Engineering at the University of Washington, Seattle, WA from 2007 to 2011.

session leader

sip-rm  Session Leader:Rahul Maneplli  Director of Engineering for Substrate Package Technology Development, Intel

Rahul Manepalli is a Sr. Principal Engineer and the Director of Module Engineering in Substrate and Package Technology Development Group in Intel Corporation. Rahul manages the Module Engineering group responsible for development of next generation Substrate and Package Technologies for all of Intel’s packaging needs. He has over 20 years of experience in Packaging (Assembly & Substrate materials, processes and modules) and has lead the startup and development of multiple Intel factories and Technology Development teams. He holds over 40 + worldwide patents in the area of electronic packaging and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.

session leader

sip-jk  Session Leader: Jingkun Mao  Vice General Manager, SRCT Tec

1998 and 2000, respectively. He received his Ph.D. degree in Electrical Engineering from the University of Missouri-Rolla in 2004. From 2004 to 2009, he worked for Amkor Technology Inc., Phoenix, AZ, as a RF Packaging Engineer. Then, he joined the Third Research Institute of MPS, as a Director of Engineer. In July 2012, he joined the SRCT Tech. Co. Ltd, currently serves as the vice general manager. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction,differential signaling, and package designs.