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Package Solution
Metis – Fast Package and IC Co-simulation


Metis provides an efficient way to extract package models with its 3D accelerated Method of Moments (MoM) electromagnetic solver. The desired nets from bump to BGA ball in a package can be easily extracted. With its IC-package assembly capability, Metis enables the IC-package co-simulation, which helps IC designers to assess the package impact easily. Metis can be also used for advanced packaging such as 2.5D interposer with Through Silicon Via (TSV).

2.5D Interposer with TSV

IC-Package Co-Simulation


  • While Moore's Law continues driving transistor scaling, heterogeneous integration enabled by 2.5D silicon interposer and HBM becomes the norm for next generation HPC applications.

  • Silicon interposer with RDL and Through-Silicon-Via (TSV) sitting between IC and package requires cross-domain solution to tackle the signal integrity problems.

  • Xpeedic provides a complete solution to design 2.5D silicon interposer with HBM for HPC applications.

  • TmlExpert: help designer to study transmission line configuration in pre-layout stage, microstrip vs stripline, SGS vs coplanar ground, line-spacing for target impedance, etc.

  • Metis: accurate and efficiently extract interconnect model for both HBM and die-package TSV channels.

  • ChannelExpert: help designer to quickly build high speed channel and run channel simulation check the standard compliance.

  • Metis offers a fast way to enable IC-package co-simulation. Not only it is easy to assemble the IC and package together for co-simulation, but also its state-of-the-art fast solver engine gives order of magnitude speedup compared to competitor solutions. Benchmark examples demonstrate the accuracy and speed of the Metis solver.

Main Features

Transmission Line Design

  • TmlExpert has built-in interposer transmission line template to help designers to explore various different configurations in terms of impedance, loss, delay, skew, and TDR.

Interconnect Model Extraction

  • Metis can extract interconnect model for both HBM and die-package TSV channels using one single solver without error-prone cut-and-stitch.

  • It supports both GDS and ODB++ format.

HBM Routing: SGS (Signal-Ground-Signal)

  • Signal channels are designed in M1 and M3 layers for different HBM channels. Meshed ground uses M2 layer.

HBM Routing: CPG (Co-Planar Ground)

  • Ground traces are in the same layer as signal traces, acting as the ground shielding wall. However, those ground traces between signal traces on the same layer will enlarge the area of interposer for the fixed number of signal lines.

Die-Package Channel with TSV

  • Die-package channel with TSV is critical for channel performance due to the loss and crosstalk introduced by the TSVs. Metis can accurately extract the model for the die-package channel.

Channel Simulation with ChannelExpert

  • ChannelExpert offers SI engineers a quick way to build channel based with the interconnect models extracted from Metis. By running the channel simulation, designers can check the performance with the built-in compliance and then optimize the channel.

IC-Package Co-Simulation Example

  • The IC-Package Co-simulation flow integrates IRIS, iModeler and Metis for analysis of IC/package coupling, signal integrity performance. Fast, easy to create wire bond or flip chip model 20x fast than conventional approaches, using accurate solver, to ensure engineer intent for signal quality is full achieved.


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