GTC2018

Xpeedic to Exhibit at GTC USA 2018

Date: September 25, 2018

Place: Santa Clara, CA

As a valuable GLOBALFOUNDRIES EDA partner, Xpeedic Technology will showcase its latest solutions at GTC USA 2018 (GLOBALFOUNDRIES Technology Conference) in Santa Clara, September 25, 2018.

Featured as in-booth demos will include

GTC AD

  • Combined IRIS-HFSS Flow for EM simulation in GLOBALFOUNDRIES Process Nodes

This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.

  • Integrated Passived Device Technology for RF Front End Design

IPD is a core technology for implementing highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and process, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are widely used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can also integrate its unique IPD into SiP and achieve even higher integration. Thanks to its proprietary EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

For more information, please visit here.

Banner-SOI

Xpeedic to Present at the 6th Shanghai FD-SOI Forum and 2018 RF-SOI Workshop

  • Date: September 18-19, 2018
  • Place: Shanghai, China

The 6th Shanghai FD-SOI Forum & 2018 International RF-SOI Workshop will be held in Shanghai at September 18-19, 2018.

The 6th Shanghai FD-SOI Forum

The 6th Shanghai FD-SOI Forum will be focused on FD-SOI applications, products, in particular AIoT and automotive electronics. There are keynote speeches by executives from Samsung and GLOBALFOUNDRIES. The theme of this year’s Forum is Deployment of FD-SOI, for which there are two sessions: AIoT using FD-SOI and automotive electronics using FD-SOI.

Visit here for more details.

2018 International RF-SOI Workshop

The workshop will be focused on 5G connectivity and opportunity for RF-SOI industry. Keynotes speaker includes 5G carrier, system provider and device maker. They will provide insight on 5G deployment and RF-SOI readiness. The session “China RF-SOI ecosystem” will have speakers from Chinese fabless companies and foundries to talk about their progress on RF-SOI, and session “RF-SOI supply chain” will be focused on worldwide RF-SOI supply chain.

Visit here for more details.

Xpeedic has been participated the events as an active SOI Industry Consortium member. Xpeedic's passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic's IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In 2018 International RF-SOI Workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will give a presentation titled “RF-SOI for RFFE Solution: An EDA Perspective” in the China RF-SOI Ecosystem session to showcase Xpeedic's contribution.

Banner-TowerJazz

Xpeedic to Exhibit at TowerJazz TGS2018

Date: August 22, 2018

Place: Shanghai, China

 

As a valuable TowerJazz EDA partner, Xpeedic Technology will showcase its latest solutions at TGS 2018 (TowerJazz Technical Global Symposium) in Shanghai, August 22, 2018.

Featured as in-booth demos will include

TowerJazz AD_V3

  • Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced TowerJazz RF and high performance analog process nodes.

This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.

  • Integrated Passived Device Technology for RF Front End Design

IPD is a core technology for implementing highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and process, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are widely used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can also integrate its unique IPD into SiP and achieve even higher integration. Thanks to its proprietary EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

TGS is an annual global event, which facilitates customer and partner interaction with TowerJazz team and industry executives to exchange information on the latest unique and advanced solutions for next-generation ICs in today’s growing markets such as consumer, industrial, automotive, medical and aerospace and defense.

For more information, please visit here.

EPEPS 2018

Xpeedic Tutorial at EPEPS 2018

Date: Oct 14-17, 2018.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Dr. Feng Ling, CEO of Xpeedic Technology, will lead Tutorial II: EM solver technologies from chip to system: challenges and opportunities at EPEPS Sunday Tutorials.

epeps tutorials

At the same time, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

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More details to see http://www.epeps.org/

Banner- Japan SOI

Xpeedic to Present at Japan SOI Design Workshop

Date: 25 October 2018

Place: Yokohama, Japan

The SOI Industry Consortium organizes for the 4th time its annual workshop in Japan. During the two day workshop, leading companies working with SOI technologies will meet in Yokohama to discuss about designing with FD & RF SOI technologies and in Tokyo to exchange on more than Moore, with special focus on silicon photonics, MEMS & sensors, and the SOI manufacturing ecosystem.
Xpeedic is an active SOI Industry Consortium member these years. Xpeedic's passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic's IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In Yokohama workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will present at EDA/IP II session (2:30pm, Thursday, 25 October 2018) together with other leading EDA vendors, such as Synopsys, Cadence, Silvaco, to discuss RF-SOI for RFFE Solution from EDA perspective.

Click here for more details.

GTC China 2018

Xpeedic to Exhibit at GTC China 2018

Date: November 1, 2018

Place: Shanghai, China

As a valuable GLOBALFOUNDRIES EDA partner, Xpeedic Technology will showcase its latest solutions at GTC China 2018 (GLOBALFOUNDRIES Technology Conference) in Shanghai, November 1, 2018.

Featured as in-booth demos will include

GTC AD

  • Combined IRIS-HFSS Flow for EM simulation in GLOBALFOUNDRIES Process Nodes

This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.

  • Integrated Passived Device Technology for RF Front End Design

IPD is a core technology for implementing highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and process, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are widely used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can also integrate its unique IPD into SiP and achieve even higher integration. Thanks to its proprietary EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

For more information, please visit here.

EMC

Xpeedic to Present Two Papers at IEEE EMC+SIPI 2018

Date: 7/30-8/3, 2018

Location: Long Beach, CA, US

Xpeedic will participate in the 2018 IEEE Symposium on Electromagnetic Compatibility and Signal, Power Integrity (EMC+SIPI) held at Long Beach Convention Center in California, USA on July 30-Aug 3, 2018.

Xpeedic has two papers accepted after a rigorous peer review process and will present them at the following time slots:

Fast Full Board Crosstalk Scan for Signal Integrity Sign-Off for High Speed PCB Designs

  • Time: 7/31 4:00PM
  • Author: Feng Ling (Xpeedic Technology); Kevin Cai (Cisco Systems, US); Bidyut Sen (Cisco Systems, US)

An Empirical Model for Foamed High-Speed Cable

  • Time: 8/2 4:00PM
  • Author: Xin Wu (Wandtec (Shenzhen) Optronics Technology); Feng Ling (Xpeedic Technology)

We look forward to meeting you there.

For more details, please click here.

IMS2018-1

Xpeedic to Exhibit at IMS2018 in Philadelphia

Xpeedic Technology will showcase its latest solutions at the 2018 IEEE MTT-S International Microwave Symposium (IMS) in Philadelphia, June 12-14.

Featured as in-booth demos will include

  • Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced Process Nodes.
    This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.
  • Integrating IRIS Plus in Nuhertz FilterSolutions to Enable Fast Filter Simulation.
    It presents a fast filter design flow by taking advantage of both the filter synthesis from Nuhertz FilterSolutions and the 3D full-wave electromagnetic simulation from Xpeedic IRIS Plus. Designers can use this combined single flow for fast filter prototyping without manually transferring CAD data from layout to EM simulation, thus improving the design efficiency.
  • Through Glass Via (TGV) Based Integrated Passive Device Technology for RF Front End Design
    Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. Xpeedic will introduce passive device (such as filters and diplexers) technology built with TGV, which can have less in-band insertion loss and greater out-of-band rejection yet still compact size.

X展架-IMS2018-Q.cdr

For more information, visit Xpeedic at Booth 1705 at the show.

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