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IPC PCB Design Forum

Date: March 20, 2019

Location: Booth 3300, Hall C3, Shanghai New International Expo Center

Xpeedic will present at IPC PCB Design Forum with the topic titled < Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff >.

Please click here to find the detail agenda and register.

CDNLive-US

CDNLive Silicon Valley 2019

Date: April 2-3, 2019
Location: Santa Clara Convention Center – Santa Clara, CA

CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems that transform the way people live, work, and play.

As Cadence Connections program value member, Xpeedic will demonstrate its latest EDA solutions at Designer Expo and will present the following technical paper with Cisoco.

Title: Enabling Pin Field Crosstalk Scan for High-Speed Designs

Author: Feng Ling, Xpeedic, Kevin Cai and Bidyut Sen, Cisco

Time: 9:30AM-10:10AM, April 2

Agenda at a Glance

Click here to get more details and register.

DesignCon2019

Xpeedic SI Live Demo at DesignCon2019

Hi all,

We are very glad to announce Xpeedic's high-speed signal integrity live demo series at DesignCon 2019.

The demos will focus on eight hottest topics, and will be presented by industry experts at Xpeedic booth. You will also get chance to receive the new year gifts from Xpeedic.

Signal Integrity Demo Highlights

  • IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
  • Through-Only De-embedding (TOD) and optimization based Dk/Df extraction for high-speed and wideband applications
  • Quick via modeling and optimization from connector footprint
  • Fast SI/PI simulation of 2.5D interposer with TSV
  • Fast and accurate fiber weave modeling and simulation
  • Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems
  • Web-based passive model management for SI/PI engineers

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MEET US AT

DesignCon2019   |    Booth 525

Select topics and join us!

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Xpeedic to Exhibit at DesignCon 2019

Date: Jan.29-31, 2019

Location: Santa Clara, CA

Booth#: 525

Xpeedic Technology, Inc. will exhibit at DesignCon 2019 at Santa Clara on Jan.29-31, 2019.

DesignCon is the premier conference for chip, board and systems design engineers in the high speed communications and semiconductor communities. The DesignCon Expo Hall offers the latest products and technologies in signal integrity and high-speed design for your current and future projects. You can test and compare emerging tools and technologies from top tier vendors.

At Booth 525, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

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Register now and use our promo code SPECIAL for a free Expo Pass &20% off any conference Pass!

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ICCAD 2018

Xpeedic to Exhibit at ICCAD 2018

Date: Nov.29-30, 2018

Location: Zhuhai, China

Booth#: 003-004

Xpeedic Technology, Inc. will exhibit at CSIA-ICCAD 2018 Annual Conference & Zhuhai IC Industry Innovation and Development Summit (ICCAD 2018) in Zhuhai on Nov.29-30, 2018.

ICCAD is a most important annual event for IC design industry in China. It creates a biggest platform for enterprises within China IC industry chain to exchange their expertise and to build up networks. This year, the theme is “Linking Core Power, Leading intelligence of the Great Bay Area”. In this annual general meeting, the Integrated Circuit industry, especially the opportunities and challenges faced by the IC Design industry, will be discussed in details in order to enhance innovation capability and improve the comprehensive capability of Chinese Integrated Circuit industrial chain, thereby satisfying the market demands and boosting international competence.

At booth 003-004 , Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

Dr. Wenliang Dai, co-founder, VP Engineering, will also present the leading design method “Addressing Modeling and Simulation Challenges for IC, Package and System” within EDA and IC Design Service forum on Nov.30.

For more details, please click here.

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Xpeedic to Exhibit at TowerJazz TGS2018 US

Date: November 7, 2018

Place: Santa Clara, US

 

As a valuable TowerJazz EDA partner, Xpeedic Technology will showcase its latest solutions at TGS 2018 (TowerJazz Technical Global Symposium) in Santa Clara, November 7, 2018.

Featured as in-booth demos will include

TowerJazz AD_V3

  • Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced TowerJazz RF and high performance analog process nodes.

This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.

  • Integrated Passived Device Technology for RF Front End Design

IPD is a core technology for implementing highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and process, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are widely used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can also integrate its unique IPD into SiP and achieve even higher integration. Thanks to its proprietary EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

TGS is an annual global event, which facilitates customer and partner interaction with TowerJazz team and industry executives to exchange information on the latest unique and advanced solutions for next-generation ICs in today’s growing markets such as consumer, industrial, automotive, medical and aerospace and defense.

For more information, please visit here.

GTC China 2018

Xpeedic to Exhibit at GTC China 2018

Date: November 1, 2018

Place: Shanghai, China

As a valuable GLOBALFOUNDRIES EDA partner, Xpeedic Technology will showcase its latest solutions at GTC China 2018 (GLOBALFOUNDRIES Technology Conference) in Shanghai, November 1, 2018.

Featured as in-booth demos will include

GTC AD

  • Combined IRIS-HFSS Flow for EM simulation in GLOBALFOUNDRIES Process Nodes

This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.

  • Integrated Passived Device Technology for RF Front End Design

IPD is a core technology for implementing highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and process, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are widely used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can also integrate its unique IPD into SiP and achieve even higher integration. Thanks to its proprietary EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

For more information, please visit here.