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Xpeedic to Exhibit at WSCE2020

Date: July 20-24, 2020

Place: Nanjing, China

Booth: X12


Xpeedic Technology will showcase its latest solutions at the2020 World Semiconductor Conference 2020 (WSCE) on August 26-28.

On the basis of the 2019 world semiconductor conference, the conference will further focus on the new trends, new trends and new products of the industry, provide international cooperation and exchange platform, and promote the rapid development of the semiconductor industry.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

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IC Category

On-chip passive modeling and simulation for RF and high performance analog designs for mobile, connectivity and optical applications
  • RFIC Passive Simulation
  • Analog/Mix Signal IC Passive Simulation
  • RF PDK Turn Key Solution

Package Category

Package modeling and simulation ranging from low cost packages to high performance interposer with TSV for mobile, networking and server applications

  • RFFE Module Simulation
  • Advanced Package Simulation
  • System in Package Simulation

System Category

Package and board level Signal Integrity analysis for high speed digital system designs in servers, storage and networking

  • RF PCB System Simulation
  • High Speed Digital System Simulation

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More details to see here.
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Xpeedic to Exhibit at IMS2020

Date: Aug 4-6, 2020

A Virtual Experience (Click here to enter Xpeedic Virtual Booth)

Xpeedic will showcase its latest 5G RF solution at the 2020 IEEE MTT-S International Microwave Symposium (IMS) .

Xpeedic RF solution spans from IC, filter, to package. Its on-chip passive modeling and simulation tool IRIS, certified by foundries, helps RFIC designers to achieve first-pass silicon success. Its package extraction tool Metis enables fast package extraction for RF SiP. Its filter design tool XDS provides a complete flow from schematic, layout, to post-layout simulation to design IPD, SAW, and BAW filters. Xpeedic RF solution further enables RF front end miniaturization with the IPD designs from spec to volume production.


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EDA-IC

IRIS enables on-chip passive modeling and simulation for RFIC designs. With its accelerated 3D EM solver, advanced process support, and seamless Virtuoso integration, IRIS helps RFIC designers to achieve first-pass silicon success.

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EDA-Package

Metis provides fast package modeling and simulation for various package types. It supports System-in-Package (SiP) which is getting more and more adoption with the 5G RF front end being more modularized. It also supports IC-package co-simulation so that package impact can be captured.

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EDA-Filter

The newly release XDS is a dedicated tool for RF filter designs. It provides a complete filter design flow from schematic to layout to post-layout co-simulation. It supports multiple filter types including IPD, SAW, and BAW. Built-in filter topology for quick schematic creation, built-in spec libraries, auto layout generation, tuning and optimization make filter designs easier.

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IP-IPD

Xpeedic advanced IPD technology to enable passive integration for 5G RF front end, helping customers to achieve faster design convergence from spec to volume production.


Xpeedic will also present at IMS MicroApps  and Industry Workshop:

MicroApps

TUMA8

Industry Workshop

IW13AB

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Xpeedic to Exhibit at DAC2020

【As the premier conference for the design and design automation of electronic circuits and systems, the 57th DAC (Design Automation Conference) program has expanded to also include many verticals closely integrated with and/or dependent on cutting-edge electronic design automation. Along with a large exhibit floor featuring top EDA, design on cloud and IP companies, stellar keynote sessions and endless networking, the topics below will be represented on both the industry and academia portions of the DAC program.】

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Date: July 20-24, 2020

A Virtual Experience

Xpeedic Technology will showcase its latest simulation-driven EDA solution from Chip, Package to System at the 2020 Design Automation Conference (DAC).

It includes the following highlights:

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1. High Speed High Frequency EDA Solution

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  IC Category

On-chip passive modeling and simulation for RF and high performance analog designs for mobile, connectivity and optical applications
  • RFIC Passive Simulation
  • Analog/Mix Signal IC Passive Simulation
  • RF PDK Turn Key Solution

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Package Category

Package modeling and simulation ranging from low cost packages to high performance interposer with TSV for mobile, networking and server applications

  • RFFE Module Simulation
  • Advanced Package Simulation
  • System in Package Simulation

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System Category

Package and board level Signal Integrity analysis for high speed digital system designs in servers, storage and networking

  • RF PCB System Simulation
  • High Speed Digital System Simulation

2. Foundry Technology Support

Xpeedic EDA supports mainstream foundry nodes, including:

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3. Xpeedic Cloud Platform on AWS

The Xpeedic Cloud Solution built on Amazon Elastic Compute Cloud (EC2) supports a wide range of instant types including both compute-optimized types and memory-intensive types. Xpeedic’s EM solver technologies support both multi-core parallelism and distributed computing, making them very suitable for cloud computing. Moreover, Xpeedic’s own job scheduler JobQueue manages the computer resource as well as prioritizes the simulation jobs. With the near infinite amount of resources available in the AWS cloud, Xpeedic can now help its customers better achieve scalability for their most demanding simulation jobs.

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Register online to get a free pass now.

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Xpeedic to Exhibit at DesignCon 2020

  • Date: Jan.28-30, 2020
  • Location: Santa Clara, CA
  • Booth#: 645

Xpeedic Technology, Inc. will exhibit at DesignCon 2020 at Santa Clara on Jan.28-30, 2020.

DesignCon is the premier conference for chip, board and systems design engineers in the high speed communications and semiconductor communities. The DesignCon Expo Hall offers the latest products and technologies in signal integrity and high-speed design for your current and future projects. You can test and compare emerging tools and technologies from top tier vendors.

At Booth 645, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

Live Demo Highlights include:


What’s more, Xpeedic, together with Cisco, will jointly publish a paper entitled HIGH-SPEED DIFFERENTIAL VIA CHARACTERIZATION: NUMERICAL SIMULATION & MEASUREMENT VALIDATION WITH DE-EMBEDDING. Details are as follows:

  • Time: Thursday, January 30 | 2:50pm – 3:30pm
  • Speakers: Anna Gao (Cisco Systems, Inc.), Feng Ling (Xpeedic Technology, Inc.)
  • Authors: Kevin Cai (Cisco Systems, Inc.), Bidyut Sen (Cisco Systems, Inc.), Joshua Wan (Xpeedic Technology, Inc.)
  • Location: Ballroom E
  • Track: 13. Modeling & Analysis of Interconnects, 12. Applying Test & Measurement Methodology

Click here to register now and use Xpeedic’s exclusive VIP registration code “SPECIAL” to get 20% off the full price.

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Xpeedic to Exhibit at TGS 2019 – US

  • Date: November 20, 2019
  • Place: Santa Clara, CA, US

As a valuable TowerJazz EDA partner, Xpeedic Technology will showcase its latest solutions at TGS US 2019 (TowerJazz Technical Global Symposium) in Santa Clara, CA, November 20, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in TowerJazz Advanced Nodes

As Moore’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by TowerJazz RF SOI TPS90 node and SiGe BiCMOS SBC18 node and widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

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Xpeedic to Exhibit at GTC 2019 – China

  • Date: October 24, 2019
  • Place: Shanghai, China

As a valuable GLOBALFOUNDRIES RFwave and FDXcelerator program partner, Xpeedic Technology will showcase its latest solutions at GTC China 2019 (GLOBALFOUNDRIES Technology Conference) in Shanghai, China, October 24, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in GF’s Advanced Nodes

As Morre’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by GLOBALFOUNDRIES FD-SOI 22FDX and FinFET 12LP Process widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (Silicon, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and service

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Samsung SAFE Foundry Forum 2019 – San Jose

Date: Oct 17, 2019

Place: San Jose, CA


As Samsung Advanced Foundry Ecosystem (SAFE™) partner, Xpeedic will be exhibiting at Samsung Foundry Forum at the San Jose, CA on Oct 17, 2019.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool

Certified on Samsung’s advanced process nodes including its FD-SOI 28FDS and 14nm FinFET node

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

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See the event details here.

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Xpeedic to Exhibit at GTC 2019 – US

  • Date: September 24, 2019
  • Place: Santa Clara, CA, US

As a valuable GLOBALFOUNDRIES RFwave and FDXcelerator program partner, Xpeedic Technology will showcase its latest solutions at GTC US 2019 (GLOBALFOUNDRIES Technology Conference) in Santa Clara, CA, September 24, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in GF’s Advanced Nodes

As Morre’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by GLOBALFOUNDRIES FD-SOI 22FDX and FinFET 12LP Process widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (Silicon, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and serviceFin