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Date: May 14, 2019, 1pm-7pm
Place: Santa Clara Marriott, Santa Clara, CA
As Samsung Advanced Foundry Ecosystem (SAFE™) partner, Xpeedic will be exhibiting at Samsung Foundry Forum at the Santa Clara Marriott, Santa Clara, CA on May 14, 2019.
Featured as in-booth demos will include
- IRIS, Virtuoso-integrated EM simulation tool
Certified on Samsung's advanced process nodes including its FD-SOI 28FDS and 14nm FinFET node
- Metis, IC-package co-simulation tool
IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.
See the event details here.
Date: April 2-3, 2019
Location: Santa Clara Convention Center – Santa Clara, CA
CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems that transform the way people live, work, and play.
As Cadence Connections program member, Xpeedic will demonstrate its latest EDA solutions at Designer Expo and will present the following technical paper.
Title: Enabling Pin Field Crosstalk Scan for High-Speed Designs
Author: Feng Ling, Xpeedic, Kevin Cai and Bidyut Sen, Cisco
Time: 9:30AM-10:10AM, April 2
Agenda at a Glance
Tuesday - April 2
Wednesday - April 3
|8:00am-9:30am||Breakfast / Registration||Breakfast / Registration|
|9:30am-10:10am||Breakout Sessions||Breakout Sessions|
|12:00pm-1:30pm||Lunch / Designer Expo||Lunch / Designer Expo|
|1:30pm-5:00pm||Breakout Sessions||Breakout Sessions|
|5:00pm-6:30pm||Reception / Designer Expo||Closing Reception / Best Presentation Awards|
Date: March 20, 2019
Location: Booth 3300, Hall C3, Shanghai New International Expo Center
Xpeedic will present at IPC PCB Design Forum with the topic titled < Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff >.
Please click here to find the detail agenda and register.
We are very glad to announce Xpeedic's high-speed signal integrity live demo series at DesignCon 2019.
The demos will focus on eight hottest topics, and will be presented by industry experts at Xpeedic booth. You will also get chance to receive the new year gifts from Xpeedic.
Signal Integrity Demo Highlights
- IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
- Through-Only De-embedding (TOD) and optimization based Dk/Df extraction for high-speed and wideband applications
- Quick via modeling and optimization from connector footprint
- Fast SI/PI simulation of 2.5D interposer with TSV
- Fast and accurate fiber weave modeling and simulation
- Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
- Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems
- Web-based passive model management for SI/PI engineers
MEET US AT
DesignCon2019 | Booth 525
Select topics and join us!
Date: Jan.29-31, 2019
Location: Santa Clara, CA
Xpeedic Technology, Inc. will exhibit at DesignCon 2019 at Santa Clara on Jan.29-31, 2019.
DesignCon is the premier conference for chip, board and systems design engineers in the high speed communications and semiconductor communities. The DesignCon Expo Hall offers the latest products and technologies in signal integrity and high-speed design for your current and future projects. You can test and compare emerging tools and technologies from top tier vendors.
At Booth 525, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.
Register now and use our promo code SPECIAL for a free Expo Pass &20% off any conference Pass!
Date: Nov.29-30, 2018
Location: Zhuhai, China
Xpeedic Technology, Inc. will exhibit at CSIA-ICCAD 2018 Annual Conference & Zhuhai IC Industry Innovation and Development Summit (ICCAD 2018) in Zhuhai on Nov.29-30, 2018.
ICCAD is a most important annual event for IC design industry in China. It creates a biggest platform for enterprises within China IC industry chain to exchange their expertise and to build up networks. This year, the theme is “Linking Core Power, Leading intelligence of the Great Bay Area”. In this annual general meeting, the Integrated Circuit industry, especially the opportunities and challenges faced by the IC Design industry, will be discussed in details in order to enhance innovation capability and improve the comprehensive capability of Chinese Integrated Circuit industrial chain, thereby satisfying the market demands and boosting international competence.
At booth 003-004 , Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.
Dr. Wenliang Dai, co-founder, VP Engineering, will also present the leading design method “Addressing Modeling and Simulation Challenges for IC, Package and System” within EDA and IC Design Service forum on Nov.30.
For more details, please click here.