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EPEPS 2020

Date: Oct 5-7, 2020
Virtual Event

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Xpeedic will showcase its latest update in 5G solution and high speed signal integrity (SI) solution in the conference. Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

IC Category

On-chip passive modeling and simulation for RF and high performance analog designs for mobile, connectivity and optical applications
  • RFIC Passive Simulation
  • Analog/Mix Signal IC Passive Simulation
  • RF PDK Turn Key Solution

Package Category

Package modeling and simulation ranging from low cost packages to high performance interposer with TSV for mobile, networking and server applications

  • RFFE Module Simulation
  • Advanced Package Simulation
  • System in Package Simulation

System Category

Package and board level Signal Integrity analysis for high speed digital system designs in servers, storage and networking

  • RF PCB System Simulation
  • High Speed Digital System Simulation

More details to see http://www.epeps.org/

EPEPS 2018

Xpeedic Tutorial at EPEPS 2018

Date: Oct 14-17, 2018.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Dr. Feng Ling, CEO of Xpeedic Technology, will lead Tutorial II: EM solver technologies from chip to system: challenges and opportunities at EPEPS Sunday Tutorials.

epeps tutorials

At the same time, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

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More details to see http://www.epeps.org/

EMC

Xpeedic to Present Two Papers at IEEE EMC+SIPI 2018

Date: 7/30-8/3, 2018

Location: Long Beach, CA, US

Xpeedic will participate in the 2018 IEEE Symposium on Electromagnetic Compatibility and Signal, Power Integrity (EMC+SIPI) held at Long Beach Convention Center in California, USA on July 30-Aug 3, 2018.

Xpeedic has two papers accepted after a rigorous peer review process and will present them at the following time slots:

Fast Full Board Crosstalk Scan for Signal Integrity Sign-Off for High Speed PCB Designs

  • Time: 7/31 4:00PM
  • Author: Feng Ling (Xpeedic Technology); Kevin Cai (Cisco Systems, US); Bidyut Sen (Cisco Systems, US)

An Empirical Model for Foamed High-Speed Cable

  • Time: 8/2 4:00PM
  • Author: Xin Wu (Wandtec (Shenzhen) Optronics Technology); Feng Ling (Xpeedic Technology)

We look forward to meeting you there.

For more details, please click here.

EPEPS 2017

EPEPS 2017

Date: Oct 15-18, 2017.
Location: San Jose, CA, US

EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

More details to see http://www.epeps.org/

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EPEPS 2016

Date: Oct 23-26, 2016.
Location: San Diego, CA, US
EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.
Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.
More details to see http://www.epeps.org/

edaps2015

Xpeedic to Exhibit at EDAPS 2015

Date: Dec 14-16, 2015.
Location: COEX, Seoul, Korea

The IEEE Electrical Design of Advanced Packaging and Systems (EDAPS) Symposium is the premier international conference in Asia Pacific region to share the recent progress of modeling, simulation and measurement for the electrical design issues on chip, package and system levels. The technical program of the symposium not only addresses the current technical issues but also brings out the challenges facing IC design, SiP/SoP packaging, EMI/EMC, EDA tools and most importantly the challenge issues in advanced 3D-IC and TSV design. As in the previous events over a decade, the EDAPS 2015 will provide a major platform for researchers from academia and industry to exchange their knowledge and to build up networks.

Xpeedic will showcase its latest technology on EDA software, IPD and SiP solution. Xpeedic EDA software tools enables fast electromagnetic modeling and extraction. The IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.

More details to see www.edaps2015.org

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EPEPS 2015

Date:Oct 25-28, 2015.
Location: San Jose, CA

Xpeedic to Exhibit at EPEPS 2015
EPEPS (Electrical Performance of Electronic Packaging and Systems) is the premier international conference on advanced and emerging issues in electrical modeling, analysis and design of electronic interconnections, packages and systems. It also focuses on new methodologies and design techniques for evaluating and ensuring signal, power and thermal integrity in high-speed designs.

Xpeedic will showcase its latest technology on EDA software, IPD and SiP solution. Xpeedic EDA software tools enables fast electromagnetic modeling and extraction. The IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.

More details to see http://www.epeps.org/

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EPEPS 2014

Date:Oct 26-29, 2014.

Location: Portland, Oregon

Xpeedic Technology, Inc. will exhibit at EPEPS 2014 Portand, Oregon on Oct 26-29, 2014. Xpeedic will showcase EDA software, IPD and SiP solution. The EDA software tools enables fast electromagnetic modeling and extraction. The IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.
More details to see http://www.epeps.org/

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Xpeedic At IEEE EDAPS 2011

Suzhou, China — Nov. 28, 2011
 
Xpeedic Technology, Inc. will at IEEE EDAPS 2011, being held at Hangzhou, China on Dec. 12-14, 2011. Feng Ling, Founder/CEO of Xpeedic Technology, Inc. will organize a special workshop “EDA Solution for Chip, Package, and Board Designs”. Leading EDA vendors will present their solutions on various topics including TSV modeling, SI/PI simulation, co-simulation, and channel analysis. Dr. Wenliang Dai, VP of Engineering of Xpeedic Technology, Inc.,  will deliver the speech titled “Enabling Optimal Channel Performance by Interconnect Tuning”.