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SiP Conference China 2019

  • Date: Sept 10-11, 2019
  • Place: Shenzhen, China

SiP Conference China 2019 is the third System-in-Package (SiP) conference in China fully dedicated to covering all aspects related to SiPs business and technology to meet current and future SiP challenges. The conference features inspiring sparkers from entire SiP supply and design chain from OEM, Fabless, IDM, OSAT, EMS, EDA, silicon foundries, equipment and material suppliers together to one place in Shenzhen, China.

The arrival of 5G and Artificial intelligent (AI) technology is having a massive impact on wireless, IoT, autonomous and connected vehicles, automated smart cities, base stations, data storage, computing and networking. The conference and exhibition will highlight System in Package technologies that are helping to implement cost effective solutions of electronic components integration in small size SiP packaging. The program will include several keynote speakers and technical sessions, followed by a panel discussion of key issues, including SiP assembly and test, advancement in materials and substrates and system solutions for targeted market applications.

The conference will cover the following vital topics:

  • SiP Business and Technology Trends
  • SiP System Solutions for Smartphone and IoT
  • 5G NR & mmWave SiP Solutions
  • 2.5D/3D and WLSiP Applications, Assembly and Test Challenges
  • Advance Material & Substrate Solutions for SiP
  • provide dynamic learning and technology updates for SiP related trends

Dr.Feng Ling, CEO of Xpeedic Technology will lead the session during the conference. Dr. Wenliang Dai, co-founder, VP Engineering, will present “Enabling SiP Design with Differentiating Simulation Technologies” within SiP Design Challenges forum on Sept.11. Xpeedic team will also demonstrate its latest SiP, IPD and related EDA solutions and products then.

 For more details, please click here.  General chair

sip-nk  General Chair:Nozad Karim  VP, Product Line SiP, Amkor Technology

Nozad Karim presently is the Vice President of SiP & System Integration at Amkor Technology. He has over 20 years’ experience with SiP & module technology developments, and over 30 years of experience working with semiconductor packaging, circuit and system designs for digital, analog, and RF/Microwave applications. Prior to Amkor, he served in engineering and management roles with Motorola Communication, Texas Instruments, & Compaq Computer.

Technical chair

sip-dv  Techinical Chair:David Lu  VP, New Technology Research Institute vivo Mobile Communication Co., Ltd.

With over 25+ years experience in electronics process engineering, material science and technology strategic planning, David is leading innovative assembly technology development for high volume manufacturing operation of consumer electronics, including smartphones, smartwatches, SiP modules, automotive modules, tablets, PC, etc. David has spent many years on Design for Manufacturing (DFM), developed DFX design guidelines, wrote assembly process specifications & standards, established NPI (New Product Introduction) verification facilities and audited EMS outsourcing. Prior to Huawei, David also held a several senior and principal technical positions in Nokia Mobile Phones, Nortel Networks and Alcatel. David is also holding several technology patents in US, Europe and China, leading industrial consortium and external technology collaboration and actively providing keynote presentations and speeches in conferences, seminar and training courses with international background and East-meets-West culture & multi-language capabilities.

Technical chair

sip-rb  Technical Chair:Rozalia Beica  VP of Technology, IMAPS

Rozalia Beica is currently Global Director Strategic Marketing with DowDuPont. She is focusing on strategic activities, identifying new technologies and markets, growth opportunities across Electronics & Imaging Division. She has 25 years of international working experience across various industries, including industrial, electronics and semiconductors. For 18 years she was involved in the research, applications and strategic marketing of Advanced Packaging, with global leading responsibilities at specialty chemicals (Rohm and Haas), equipment (Semitool, Applied Materials and Lam Research) and device manufacturing (Maxim IC). Prior to joining Dow, Rozalia was the CTO of Yole Developpement where she led the market research, technology and strategy consulting activities for Advanced Packaging and Semiconductor Manufacturing.

session leader

sip-fl  Session Leader: Feng Ling  CEO, Xpeedic Technology

Feng Ling (S’97-M’00-SM’07) is currently Founder and CEO of Xpeedic Technology, Inc., a leading EDA software and IP provider in chip-package-system solution. In 2000, he was a Senior Staff Engineer/Scientist at Motorola (now Freescale Semiconductor), working on RF module technology with LTCC and HDI substrate. In 2002, he joined Neolinear, where he led the electromagnetic solver development for mixed-signal RF integrated circuit designs. Through Cadence acquisition of Neolinear, he joined Cadence in 2004. As VP of Engineering, he co-founded Physware in 2007 (acquired by Mentor Graphics in 2014). In 2010, he founded Xpeedic Technology, Inc., continuing the efforts to bring the novel solution to the RF design and high speed digital community. Dr. Ling received his Ph.D. degree in electrical engineering from the University of Illinois at Urbana-Champaign (UIUC) in 2000. He is a Senior Member of IEEE. He has authored and co-authored 2 book chapters and more than 60 papers in refereed journals and conference proceedings. He has served on the technical program committee of DesignCon, EDAPS, and EPTC. He has 5 US patents. He was the inaugural recipient of the Y. T. Lo Outstanding Research Award from the Department of Electrical and Computer Engineering at UIUC in 1999. He has been an Affiliate Associate Professor in the Department of Electrical Engineering at the University of Washington, Seattle, WA from 2007 to 2011.

session leader

sip-rm  Session Leader:Rahul Maneplli  Director of Engineering for Substrate Package Technology Development, Intel

Rahul Manepalli is a Sr. Principal Engineer and the Director of Module Engineering in Substrate and Package Technology Development Group in Intel Corporation. Rahul manages the Module Engineering group responsible for development of next generation Substrate and Package Technologies for all of Intel’s packaging needs. He has over 20 years of experience in Packaging (Assembly & Substrate materials, processes and modules) and has lead the startup and development of multiple Intel factories and Technology Development teams. He holds over 40 + worldwide patents in the area of electronic packaging and has a Ph.D. in Chemical Engineering from the Georgia Institute of Technology.

session leader

sip-jk  Session Leader: Jingkun Mao  Vice General Manager, SRCT Tec

1998 and 2000, respectively. He received his Ph.D. degree in Electrical Engineering from the University of Missouri-Rolla in 2004. From 2004 to 2009, he worked for Amkor Technology Inc., Phoenix, AZ, as a RF Packaging Engineer. Then, he joined the Third Research Institute of MPS, as a Director of Engineer. In July 2012, he joined the SRCT Tech. Co. Ltd, currently serves as the vice general manager. His research interests include signal integrity and EMI designs in high-speed digital systems, dc power-bus modeling, intra-system EMI and RF interference, PCB noise reduction,differential signaling, and package designs.

  

Banner-IMS2019

Xpeedic to Exhibit at IMS2019

Date: June 2-7, 2019

Place: Boston, US

Booth#: 210


Xpeedic Technology will showcase its latest solutions at the 2019 IEEE MTT-S International Microwave Symposium (IMS) in Boston Convention & Exhibition Center, June 2-7.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver

Certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

  • IPD for RF FE module design

Advanced IPD technology to enable passive integration for RF front end, helping customers to achieve faster design convergence from spec to volume production.

  • Through Glass Via (TGV) solution in collaboration with Corning

Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. A diplexer built with TGV shows less in-band insertion loss and greater out-of-band rejection yet still compact size.


Xpeedic will also present at IMS MicroApps Theatre

* Title: Integrated Passive Devices (IPD) for RF Front End Integration (WEMA35)

* Time: June 5, 12:30-12:45

See the event details here.

IMS2019-2

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Xpeedic to Exhibit at DAC2019

Date: June 2-6, 2019

Place: Las Vegas, NV, US

Booth#:622

Xpeedic Technology will showcase its latest solutions at the 2019 Design Automation Conference (DAC) in Las Vegas, June 2-6.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

dac-5g

5G RFIC in Advanced Process Nodes
  • IRIS,Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver, certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

IC-Package Co-design for 5G Application
  • Metis,IC-package co-simulation tool to enable 5G system-in-package designs, and supports advanced packaging technologies for CPU, GPU, network processor, FPGA designs to enable artificial intelligence applications in 5G era.

Integrated Passive Devices for 5G NR
  • RF front end module has become more and more complicated with mobile technology evolving from 2G, 3G, 4G to 5G. Increasing number of bands, carrier aggregation, and MIMO demand more filters and more integration in RF front end. Integrated passive devices (IPD) provide great advantages of miniaturization, high consistency, low cost and high integration over discrete. Xpeedic has partnered with industry leading IPD foundries with both silicon and glass substrates. With the extensive IPD design experience,Xpeedic helps customers to choose the right technology to meet their spec.

More details to see here.

Banner-WSC2019

Xpeedic to Exhibit at WSC2019

日期:2019年5月17-19日
地点:南京,国际博览会议中心
展位号:E1

2019世界半导体大会暨第十七届中国半导体市场年会即将于5月17-19日在南京国际博览会议中心开幕。

本届大会以创新协作、世界同“芯”为主题,全方位展示半导体产业的发展动态和最新成果,促进积极有效的交流合作;大会将采用“2+N+1”的举办模式,举办2场主论坛(高峰论坛和创新峰会),N场专题论坛/专题活动以及1场专业展会;大会还将公布“第十三届(2018年度)中国半导体创新产品和技术项目”,发布《世界半导体市场趋势展望白皮书》、《中国半导体产业发展状况白皮书》等相关评选结果与专题报告。

芯禾科技在本届大会上将主要展示其EDA/IP整合解决方案的最新研发成果,包括EDA设计仿真工具、无线射频IPD集成无源器件和SiP系统级封装服务的三大产品线。

WSC2019-2

WSC2019-1

现场演讲:

大会期间,芯禾科技还将在本次大会上带来两篇论坛演讲,分别是

EDA Enablement for RF- and FD-SOI

  • SOI论坛
  • 5/18 15:55
  • CEO 凌峰博士

《仿真驱动EDA解决方案助力先进IC-封装-系统设计》

  • EDA/IP设计服务论坛
  • 5/18 16:00
  • 副总裁 代文亮博士

大会的详细日程安排如下:

日程表
扫描二维码报名参会
报名二维码

Banner-MWC2019

MWC 2019

一年一度的 MWC 世界移动通信展会2/25-2/28在巴塞罗那如火如荼的举行。这期间,各大厂商们“蓄谋已久”的年度大招频出,这些技术将对如今越来越同质化的手机通信市场带来耳目一新的新鲜元素,并引领整个行业革新和创新趋势。微信图片_20190227101147

特殊玻璃行业的全球领导厂商康宁公司联合芯禾科技,在本次大会上发布了针对5G射频前端模组和Wifi应用的玻璃通孔(ThroughGlass Vias, TGV)解决方案。

微信图片_20190227101153

当前移动和物联网设备市场正经历着爆发式的增长。尽管数字电路在摩尔定律的驱动下继续增加着集成度,但射频电路却无法按相同比例减小尺寸。因此射频电路尤其是无源器件部分的进一步集成,成为系统小型化的关键。

为了满足不断增长的小型化需求,在增加功能的同时减小尺寸、降低成本,集成无源器件(IPD)技术已成为射频前端设计的一种令人期待的先进技术,它也已经从低温共烧陶瓷(LTCC)发展到薄膜技术,如使用高阻硅(HRSi)或玻璃基板。在最新的研发进程中,玻璃通孔技术已被视为实现集成、低成本和高性能无源器件最有前途的技术之一。

微信图片_20190227101158

芯禾科技的TGV解决方案具有多项显著优势:与二维平面电感相比,采用TGV结构的三维电感具有更好的品质因数;与硅相比,玻璃的介电常数较低,电阻率较高,因而具有较好的高频性能;诸如使用TGV构建的滤波器和双工器之类的无源器件,在确保较小的带内插损和较大的带外抑制能力的同时,还能在尺寸上做小。

微信图片_20190227101201

如果您在MWC现场,我们非常欢迎您至康宁公司展位(Hall 2 Executive Meeting Rooms, Upper Level, Room #2G9Ex)了解详情

DesignCon2019

Xpeedic SI Live Demo at DesignCon2019

Hi all,

We are very glad to announce Xpeedic’s high-speed signal integrity live demo series at DesignCon 2019.

The demos will focus on eight hottest topics, and will be presented by industry experts at Xpeedic booth. You will also get chance to receive the new year gifts from Xpeedic.

Signal Integrity Demo Highlights

  • IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
  • Through-Only De-embedding (TOD) and optimization based Dk/Df extraction for high-speed and wideband applications
  • Quick via modeling and optimization from connector footprint
  • Fast SI/PI simulation of 2.5D interposer with TSV
  • Fast and accurate fiber weave modeling and simulation
  • Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems
  • Web-based passive model management for SI/PI engineers

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MEET US AT

DesignCon2019   |    Booth 525

Select topics and join us!

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Banner-Designcon2019

Xpeedic to Exhibit at DesignCon 2019

Date: Jan.29-31, 2019

Location: Santa Clara, CA

Booth#: 525

Xpeedic Technology, Inc. will exhibit at DesignCon 2019 at Santa Clara on Jan.29-31, 2019.

DesignCon is the premier conference for chip, board and systems design engineers in the high speed communications and semiconductor communities. The DesignCon Expo Hall offers the latest products and technologies in signal integrity and high-speed design for your current and future projects. You can test and compare emerging tools and technologies from top tier vendors.

At Booth 525, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

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Register now and use our promo code SPECIAL for a free Expo Pass &20% off any conference Pass!

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ICCAD 2018

Xpeedic to Exhibit at ICCAD 2018

Date: Nov.29-30, 2018

Location: Zhuhai, China

Booth#: 003-004

Xpeedic Technology, Inc. will exhibit at CSIA-ICCAD 2018 Annual Conference & Zhuhai IC Industry Innovation and Development Summit (ICCAD 2018) in Zhuhai on Nov.29-30, 2018.

ICCAD is a most important annual event for IC design industry in China. It creates a biggest platform for enterprises within China IC industry chain to exchange their expertise and to build up networks. This year, the theme is “Linking Core Power, Leading intelligence of the Great Bay Area”. In this annual general meeting, the Integrated Circuit industry, especially the opportunities and challenges faced by the IC Design industry, will be discussed in details in order to enhance innovation capability and improve the comprehensive capability of Chinese Integrated Circuit industrial chain, thereby satisfying the market demands and boosting international competence.

At booth 003-004 , Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

Dr. Wenliang Dai, co-founder, VP Engineering, will also present the leading design method “Addressing Modeling and Simulation Challenges for IC, Package and System” within EDA and IC Design Service forum on Nov.30.

For more details, please click here.

IMS2018-1

Xpeedic to Exhibit at IMS2018 in Philadelphia

Xpeedic Technology will showcase its latest solutions at the 2018 IEEE MTT-S International Microwave Symposium (IMS) in Philadelphia, June 12-14.

Featured as in-booth demos will include

  • Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced Process Nodes.
    This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.
  • Integrating IRIS Plus in Nuhertz FilterSolutions to Enable Fast Filter Simulation.
    It presents a fast filter design flow by taking advantage of both the filter synthesis from Nuhertz FilterSolutions and the 3D full-wave electromagnetic simulation from Xpeedic IRIS Plus. Designers can use this combined single flow for fast filter prototyping without manually transferring CAD data from layout to EM simulation, thus improving the design efficiency.
  • Through Glass Via (TGV) Based Integrated Passive Device Technology for RF Front End Design
    Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. Xpeedic will introduce passive device (such as filters and diplexers) technology built with TGV, which can have less in-band insertion loss and greater out-of-band rejection yet still compact size.

X展架-IMS2018-Q.cdr

For more information, visit Xpeedic at Booth 1705 at the show.

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