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Xpeedic to Exhibit at TGS 2019 – US

  • Date: November 20, 2019
  • Place: Santa Clara, CA, US

As a valuable TowerJazz EDA partner, Xpeedic Technology will showcase its latest solutions at TGS US 2019 (TowerJazz Technical Global Symposium) in Santa Clara, CA, November 20, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in TowerJazz Advanced Nodes

As Moore’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by TowerJazz RF SOI TPS90 node and SiGe BiCMOS SBC18 node and widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

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Xpeedic to Exhibit at GTC 2019 – China

  • Date: October 24, 2019
  • Place: Shanghai, China

As a valuable GLOBALFOUNDRIES RFwave and FDXcelerator program partner, Xpeedic Technology will showcase its latest solutions at GTC China 2019 (GLOBALFOUNDRIES Technology Conference) in Shanghai, China, October 24, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in GF’s Advanced Nodes

As Morre’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by GLOBALFOUNDRIES FD-SOI 22FDX and FinFET 12LP Process widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (Silicon, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and service

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Samsung SAFE Foundry Forum 2019 – San Jose

Date: Oct 17, 2019

Place: San Jose, CA


As Samsung Advanced Foundry Ecosystem (SAFE™) partner, Xpeedic will be exhibiting at Samsung Foundry Forum at the San Jose, CA on Oct 17, 2019.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool

Certified on Samsung’s advanced process nodes including its FD-SOI 28FDS and 14nm FinFET node

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

SFF2019-1

See the event details here.

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Xpeedic to Exhibit at GTC 2019 – US

  • Date: September 24, 2019
  • Place: Santa Clara, CA, US

As a valuable GLOBALFOUNDRIES RFwave and FDXcelerator program partner, Xpeedic Technology will showcase its latest solutions at GTC US 2019 (GLOBALFOUNDRIES Technology Conference) in Santa Clara, CA, September 24, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in GF’s Advanced Nodes

As Morre’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by GLOBALFOUNDRIES FD-SOI 22FDX and FinFET 12LP Process widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (Silicon, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and serviceFin

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Xpeedic to Exhibit at SMIC 2019 Technology Symposium

  • Time: September 19, 2019
  • Location: Shanghai

Xpeedic Technology will be exhibiting at the SMIC 2019 Technology Symposium Shanghai on Sept. 19. Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in SMIC Advanced Nodes

As Moore’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

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Xpeedic to Exhibit at FD-SOI Forum and RF-SOI Workshop 2019

  • Date: September 16-17, 2019
  • Place: Shanghai, China

The 7th Shanghai FD-SOI Forum & 2019 International RF-SOI Workshop will be held in Shanghai at September 16-17, 2019.

The 7th Shanghai FD-SOI Forum

This 7th Shanghai FD-SOI Forum will focus on Automotive and IoT applications, products, and supply chain with AI/Edge Computing being discussed in conjunction with Automotive and IoT. There are keynote speeches by executives from Fabless and foundries. The theme of this year’s Forum is Deployment of FD-SOI, for which there are two sessions: AIoT using FD-SOI and automotive electronics using FD-SOI.

Visit here for FD-SOI event.

2019 International RF-SOI Workshop

The RF-SOI Workshop will be focused on 5G connectivity and its opportunity for SOI Industry. Keynote speaker will include 5G carrier, system provider and device maker. They will provide insight on the latest development on 5G deployment and RF-SOI readiness. In the afternoon session, there will be “China RF-SOI Ecosystem” and “RF Value Chain”. It will be focused on RF design and foundry platform for 5G RF-SOI application in China. Also worldwide SOI supply chain will be presented.

Visit here for RF-SOI event.

As an active member of SOI Industry Consortium, Xpeedic has been collaborating with members in the SOI eco-system to provide innovative EDA tools and IP solution to its customers. Xpeedic’s passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic’s IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In 2019 International RF-SOI Workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will give a presentation titled “Innovative EDA Solutions to Enable Differentiated RF-SOI Designs” in the China RF-SOI Ecosystem session to showcase Xpeedic’s contribution.

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Xpeedic to Exhibit at TGS 2019 – China

  • Date: September 03, 2019
  • Place: Shanghai, China

As a valuable TowerJazz EDA partner, Xpeedic Technology will showcase its latest solutions at TGS 2019 (TowerJazz Technical Global Symposium) in Shanghai, September 03, 2019.

Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in TowerJazz Advanced Nodes

As Moore’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes. It has been certified by GLOBALFOUNDRIES FD-SOI 22FDX and CMOS 12LP Process widely adopted by fabless design companies.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

For more information, please visit here.

CDNLive-US

CDNLive Silicon Valley 2019

Date: April 2-3, 2019
Location: Santa Clara Convention Center – Santa Clara, CA

CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems that transform the way people live, work, and play.

As Cadence Connections program member, Xpeedic will demonstrate its latest EDA solutions at Designer Expo and will present the following technical paper.

Title: Enabling Pin Field Crosstalk Scan for High-Speed Designs

Author: Feng Ling, Xpeedic, Kevin Cai and Bidyut Sen, Cisco

Time: 9:30AM-10:10AM, April 2

Agenda at a Glance

TimeDay One
Tuesday - April 2
Day Two
Wednesday - April 3
8:00am-9:30amBreakfast / RegistrationBreakfast / Registration
9:30am-10:10amBreakout SessionsBreakout Sessions
10:30am-12:00pmKeynotesBreakout Sessions
12:00pm-1:30pmLunch / Designer ExpoLunch / Designer Expo
1:30pm-5:00pmBreakout SessionsBreakout Sessions
5:00pm-6:30pmReception / Designer ExpoClosing Reception / Best Presentation Awards

Click here to get more details and register.

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IPC PCB Design Forum

Date: March 20, 2019

Location: Booth 3300, Hall C3, Shanghai New International Expo Center

Xpeedic will present at IPC PCB Design Forum with the topic titled < Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff >.

Please click here to find the detail agenda and register.