Heracles – Automated SI Signoff for High Speed Design


Crosstalk and impedance analysis for high speed PCB design becomes more and more important due to the high data rate and tightly coupled routing. Traditional circuit-based analysis can not meet the accuracy demand. Three-dimensional (3D) full-wave electromagnetic solver is required to capture the complex 3D PCB environment and the frequency-dependent phenomena. However it is prohibitively expensive to simulate the practical large board cases and the resultant tabulated S-parameter cannot be directly used to quantify the crosstalk level. Heracles integrated a novel hybrid solver techniques with improved speed and accuracy, and developed new crosstalk metrics to quantify the crosstalk level by post-processing S-parameter, and Heracles allows designers to achieve full board crosstalk in a few hours as planned intended with using the tool, which significantly reduces the post-layout review time, allows layout optimization and ensures a timely sign-off.

Product Introduction

Heracles was the first SI signoff tool for high speed designs, and integrated a novel hybrid full-wave EM solver with the same accuracy order as the conventional 3D solver but an order of magnitude faster speed is developed. The hybrid solver takes advantage of the layered nature of the PCB layout and adopts the idea of layer-by-layer decomposition to reduce the complexity of the problem and achieve the computation speed optimized for full board crosstalk scan. With automated SI signoff flow, we are able to achieve the complete full board crosstalk scan in a few hours as intended with using the tool, which significantly reduces the post-layout check time, allows layout optimization, and ensures the full board coverage.

  • Heracles is integrated in Allegro, and enable quick crosstalk scan, impedance scan and design rule check beyond Allegro.
  • Support intuitive crosstalk level display for the selected nets by table, It also maps to the layout with different colors to allow quick hotspot location identification.
  • Build-in S-parameter analysis module, qucikly check each TDR and TDT curve.
Main Features
  • Built-in versatile EM solver engines with controllable accuracy and speed to achieve full board scan within a few hours, including FEM3D solver, Hybrid Solver and Pure Via Solver
  • Built-in high speed I/O compliance such as Ethernet, PCI Express, DDR, USB, SATA and SAS, which crosstalk poses great challenges for high speed PCB designers with the ever increasing data rate
  • Provides two flexible ways to select crosstalk scan areas with potential SI issues, either by net matching rules defined in high speed I/O compliances or selected manually
  • Heracles XSE provides interactive interface to invoke ViaExpert to visualize, sweep and optimize crosstalk model, and also export to HFSS for better correlation
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