Metis provides an efficient way to extract package models with its 3D accelerated Method of Moments (MoM) electromagnetic solver. The desired nets from bump to BGA ball in a package can be easily extracted. With its IC-package assembly capability, Metis enables the IC-package co-simulation, which helps IC designers to assess the package impact easily. Metis can be also used for advanced packaging such as 2.5D interposer with Through Silicon Via (TSV).
- While Moore’s Law continues driving transistor scaling, heterogeneous integration enabled by 2.5D silicon interposer and HBM becomes the norm for next generation HPC applications.
- Silicon interposer with RDL and Through-Silicon-Via (TSV) sitting between IC and package requires cross-domain solution to tackle the signal integrity problems.
- Xpeedic provides a complete solution to design 2.5D silicon interposer with HBM for HPC applications.
- TmlExpert: help designer to study transmission line configuration in pre-layout stage, microstrip vs stripline, SGS vs coplanar ground, line-spacing for target impedance, etc.
- Metis: accurate and efficiently extract interconnect model for both HBM and die-package TSV channels.
- ChannelExpert: help designer to quickly build high speed channel and run channel simulation check the standard compliance.
- Metis offers a fast way to enable IC-package co-simulation. Not only it is easy to assemble the IC and package together for co-simulation, but also its state-of-the-art fast solver engine gives order of magnitude speedup compared to competitor solutions. Benchmark examples demonstrate the accuracy and speed of the Metis solver.