iVerifier – RF Passive PDK Verification
PDK model quality is essential for designers to design ICs with confidence. Typically PDK models are in the form of parameterized formula as function of physical parameters of the device, which are created via a mathematical data fitting process on either measured or simulated samples. The model quality is highly dependent on the number of samples and the number of terms in the fitted model. Xpeedic iVerifier provides a quick way to allow PDK engineers or IC designers to assess the PDK model quality by sweeping the model physical parameters and visualizing the model from various plots and tables. The built-in model templates offer designers an easy way to extract the electrical parameter from the model. The rich plot function allows designers to visualize the electrical parameters as function of physical parameters. Simply by examining the plots, the designers can assess the PDK model accuracy and the PDK completeness in terms of design space coverage.
Xpeedic iVerifier solution provides designers a quick way to verify PDK models in Cadence Virtuoso environment. It includes two flows, one is schematic based and the other is layout based. In iVerifier schematic flow, the PDK model test bench is run in ADE with Spectre simulator by sweeping the CDF parameters of the PDK model. In iVerifier layout flow, Xpeedic full-wave EM solver IRIS is run by sweeping the geometry parameters of PCell. iVerifier provides a quick way to analyze and visualize the results, which helps PDK engineers or IC designers to assess the model quality.