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IRIS: Fast EM Simulation with Virtuoso Integration

In high frequency silicon circuit design, passive devices, interconnect, and their mutual coupling have to be taken into account via electromagnetic (EM) simulation. Full-wave EM simulation is becoming necessary to cover the RF frequency of interest including multiple harmonics compared to quasi-static RC extraction. Cadence Virtuoso based schematic and layout flow is widely adopted for IC designers. However, lack of the built-in full-wave EM simulation tool leads to frequent transfer of the layout data between Virtuoso environment and outside EM tools, which is very manual and error-prone. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation. This design flow will greatly help IC designers to reduce the design cycles and achieve first-pass silicon success.

Please click the link below to download the file.

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iModeler: Fast PDK Model Generation

A process design kit (PDK) is a set of files used within the semiconductor industry to model a fabrication process for the design tools used to design an integrated circuit. With a PDK, designers can jump-start chip design and work through the design flow seamlessly, from schematic entry to tapeout. PDK accuracy is essential for RFIC designs and increase the chances of first-pass successfully silicon. Cadence Virtuoso based schematic and layout flow is widely adopted for RF designs. iModeler allows PDK engineers to stay in Cadence Virtuoso design environment to easily create the parameterized cells (PCells), accurate parameterized equivalent circuit SPICE model, symbols and technology files. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves PDK generation efficiency. Artificial Neural Network (ANN) based synthesis flow provides an efficient way to synthesize the passive components with +/-5% for 90% of samples, and greatly help IC designers to reduce the design cycles and achieve first-pass silicon success.

Please click the link below to download the file.

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Xpeedic to Exhibit at TowerJazz TGS2018

Date: August 22, 2018

Place: Shanghai, China

 

As a valuable TowerJazz EDA partner, Xpeedic Technology will showcase its latest solutions at TGS 2018 (TowerJazz Technical Global Symposium) in Shanghai, August 22, 2018.

Featured as in-booth demos will include

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  • Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced TowerJazz RF and high performance analog process nodes.

This flow is seamlessly integrated in Cadence Virtuoso platform, and gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage with Xpeedic accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique , but also the verification capability enabled by HFSS at the sign-off stage.

  • Integrated Passived Device Technology for RF Front End Design

IPD is a core technology for implementing highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and process, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are widely used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can also integrate its unique IPD into SiP and achieve even higher integration. Thanks to its proprietary EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.

TGS is an annual global event, which facilitates customer and partner interaction with TowerJazz team and industry executives to exchange information on the latest unique and advanced solutions for next-generation ICs in today’s growing markets such as consumer, industrial, automotive, medical and aerospace and defense.

For more information, please visit here.

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Xpeedic to Present at Japan SOI Design Workshop

Date: 25 October 2018

Place: Yokohama, Japan

The SOI Industry Consortium organizes for the 4th time its annual workshop in Japan. During the two day workshop, leading companies working with SOI technologies will meet in Yokohama to discuss about designing with FD & RF SOI technologies and in Tokyo to exchange on more than Moore, with special focus on silicon photonics, MEMS & sensors, and the SOI manufacturing ecosystem.
Xpeedic is an active SOI Industry Consortium member these years. Xpeedic’s passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic’s IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In Yokohama workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will present at EDA/IP II session (2:30pm, Thursday, 25 October 2018) together with other leading EDA vendors, such as Synopsys, Cadence, Silvaco, to discuss RF-SOI for RFFE Solution from EDA perspective.

Click here for more details.

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IRIS Plus: Fast RFIC and MMIC Passive Extraction simulation tool

Xpeedic IRIS Plus provides a 3D EM simulation tool of passive devices and interconnect structures for RF/microwave chips, modules, packages, and circuit boards. Industry leading multi-layer structure of the method of acceleration technology, fast and accurate simulation of complex electromagnetic effects, including the skin effect of the conductor, proximity effect and multiple dielectric loss. IRIS Plus support multi-thread calculation, its solver greatly reduce the EM simulation time, improve the design efficiency. IRIS Plus support import IRIS project file, GDS, DXF file, also integrate RFIC template modeling, and RFPCB template modeling. The IRIS Plus design flow will greatly reduce the IC design time of RFIC designer.

 Please click the link below to download the file.

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Integrating IRIS Plus in Nuhertz FilterSolutions to Enable Fast Filter Design

This application note presents a fast filter design flow by taking advantage of both the filter synthesis from Nuhertz FilterSolutions and the 3D full-wave electromagnetic simulation from Xpeedic IRIS Plus. The combined flow offers designers a single flow for fast filter prototyping without manually transferring CAD data from layout to EM simulation, thus improving the design efficiency.

Introduction

Radio-frequency (RF)/microwave filter is an important component in a high-frequency system. Designing such a filter for given performance specifications is often a tedious and iterative process.

Nuhertz FilterSolutions provides a quick and accurate approach for filter synthesis and analysis. It supports various filter topologies including distributed filters built on microstrip, stripline, or suspended substrate. However, the high frequency characteristics such as parasitic effect are not considered. Adding Xpeedic IRIS Plus, a 3D full-wave electromagnetic solver, into the flow can address this problem.

It is the purpose of this application note to demonstrate the advantages of combining circuit-based synthesis with EM-based simulation in RF/microwave filter design. Figure 1 shows the combined Nuhertz-Xpeedic flow to enable fast filter prototyping.

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Figure 1 Diagram showing the combined Nuhertz-Xpeedic flow.

Please click the link below to download the file.(Please make sure you login first)

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Combined IRIS-HFSS Flow for Passive Modeling and Verification in Advanced Process Nodes

This application note presents a combined IRIS-HFSS flow for passive modeling and verification in advanced process nodes, which gives IC designers not only the fast and accurate passive modeling and synthesis capability at the design stage, but also the verification capability at the sign-off stage.

Introduction

Electromagnetic simulation of passives and interconnects becomes challenging for IC designers in advanced process nodes. First, an integrated environment is required in which EM simulation tool is seamlessly integrated within the design platform. Second, fast passive modeling and synthesis is needed at the design stage. Third, the very accurate three dimensional EM simulation is desired for sign-off or IC-package co-simulation.

In this application note, a combined IRIS-HFSS flow seamlessly integrated in Cadence Virtuoso platform is demonstrated, as shown in Figure 1. At the design stage, IRIS and iModeler enable fast passive modeling and synthesis with its accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique. At the verification stage, HFSS enables accurate 3D simulation and possible IC-package co-simulation.

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Figure 1 Combined IRIS-HFSS flow for IC designers.

Please click the link below to download the file.(Please make sure you login first)

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Through Glass Via (TGV) Based Integrated Passive Device Technology for RF Front End Design

This white paper presents a comprehensive study on TGV based integrated passive devices (IPD) in the context of comparing with other IPD technologies such as low-temperature-cofired-ceramics (LTCC), high resistivity silicon (HRSi), and glass substrate. The comparison is not only on the component (inductor) level but also on the system level, where a carrier aggregation diplexer is designed. Further TGV process improvement is also suggested based on the study.

Introducion

Mobile and IoT device market has experienced tremendous growth in the past. While Moore’s law continues to drive the technology to shrink for the digital portion of the devices, the RF portion does not scale in the same rate. The further reduction in cost and size comes from the passive integration. To meet the ever growing demand reduce size and cost, increase functionality, integrated passive device (IPD) technology has become a viable technology for RF front end designs. It has evolved from low-temperature cofired ceramics (LTCC) to thin-film technologies such as the one using high-resistivity silicon (HRSi) or glass substrate.

Recently, Through Glass Via (TGV) technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. Three-dimensional solenoid inductors can be constructed with TGVs for better quality-factor compared with 2D planar inductors. Glass’s lower dielectric constant and higher resistivity compared to silicon lead to better high frequency performance. Passive devices such as filters and diplexers built with TGV can have less in-band insertion loss and greater out-of-band rejection yet still compact size.

This white paper will demonstrate the TGV performance by comparing TGV inductor with those built on LTCC, HRSi, and glass substrate. The similar comparison is also carried out on system level. A carrier aggregation (CA) diplexer is designed with TGV, LTCC, HRSi and glass, respectively. Their performance such as IL, isolation, and attenuation is compared. Further improvement on TGV performance is studied from the TGV process perspective.

Please click the link below to download the file.(Please make sure you login first)

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Xpeedic to Present at Samsung Foundry’s DAC Theater

Date: June 25 Monday 3:30pm

Place: San Francisco, CA, US

As a partner of Samsung Advanced Foundry Ecosystem (SAFE) program, Xpeedic is invited to present at Samsung Foundry’s DAC 2018 Theater. Dr. Feng Ling, Founder and CEO of Xpeedic, will give the presentation titled  Accurate Passive Modeling and Simulation for Advanced Process Nodes  at Samsung’s booth.

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As we move to advanced process nodes, electromagnetic simulation of passives and interconnects becomes challenging for IC designers. In the presentation, Xpeedic IRIS flow with seamless integration in Cadence Virtuoso platform will be demonstrated. At the design stage, IRIS and iModeler enable fast passive modeling and synthesis with its accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique. Through the collaboration between Xpeedic and Ansys, IRIS has a direct link to Ansys’s 3D Finite Element Method (FEM) based HFSS to enable passive simulation verification at the signoff stage. This link also makes the simulation of arbitrarily shaped 3D structures and IC-package co-simulation possible.

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During DAC 2018, Xpeedic will bring a series of demos covering simulation from IC, package, to system at its DAC booth# 2041, including the IRIS flow for passive modeling and simulation in advanced nodes, IRIS for both high-resistivity silicon (HRSi) and through-glass-via (TGV) based IPD design, Hermes for 3D package simulation, and expert-series signal integrity tools for high speed systems.

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We look forward to meeting you there.

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Xpeedic’s IRIS Certified for EM Simulation in GF 22FDX Process

Cupertino, CA. — June 12, 2018 —Xpeedic Technology, Inc. today announced that its 3D full-wave electromagnetic (EM) simulation tool, IRIS, has been certified in GLOBALFOUNDRIES’ 22FDX® process technology. This certification enables designers to run IRIS with confidence using the certified IRIS process file available in GF’s 22FDX PDK.

Xpeedic’s IRIS is empowered by an accelerated Method of Moments solver engine to achieve both accuracy and scalability for large-scale structures. For advanced nodes, it takes into account the width- and spacing-dependent process variations such as resistance table and bias table. As a result, IRIS is able to capture the conductor skin effect and proximity effect to accurately simulate passive components like inductors and MOM (metal-oxide-metal) capacitors. Xpeedic has done extensive simulation on various inductors and MOM capacitors with different process stack options. Excellent correlation with silicon measurement has been achieved.

“We are very pleased that IRIS is able to achieve excellent correlation with measurement and thus certified for GF’s 22FDX process,” said Dr. Feng Ling, CEO of Xpeedic Technology, “With its powerful EM solver engine and seamless integration in design environment, IRIS can greatly help IC designers to shorten the design cycles and achieves first-pass silicon success.”

The electromagnetic certification program by GF ensures that every EM tool certified by the program meets the highest quality standards. With this certification, IC designers can choose their preferred EM simulation tool and its corresponding process file to ensure their design confidence and reduce time-to-market.