Posts

Xpeedic 2018_iModeler

EDA Release – New Upgrade – iModeler 2018

We are glad to announce that Xpeedic released the passive PDK Model Generation —— iModeler 2018 this month.

iModeler 2018 provides RFIC designers a fast solution for RF passive design in Cadence Virtuoso platform. The solution employs a full-wave 3D EM solver with both multi-core and distributed parallelization feature that greatly reduces the EM simulation time. It includes several types of tools for modeling and parameter extraction which can deal with most cases. This software will make RF passive device design easier and increase the efficiency.

What’s new in iModeler 2018

  • Support bias table and rho table in iModeler to account for technology variations for advanced IC nodes.
  • Support PCell synthesis database buildup based on Artificial Neural Network (ANN) algorithm for PDKtoModel flow.
  • Add interleave transformer and splayed inductor templates to quick create PCell and parameterized equivalent circuit.
  • Support create PCell only flow without run EM simulation.
  • Support Equivalent Circuit generation for each new iCell generated from sweep table.
  • Add “Abort All” button to stop iModeler batch EM simulation defined in sweep table.
  • Reduce iModeler simulation options to simplify IRIS usage and give better user experience.
Xpeedic 2018_IRIS

EDA Release – New Upgrade – IRIS 2018

We are glad to announce that Xpeedic released the RFIC Passive Extraction —— IRIS 2018 this month.

IRIS 2018 obtained the GF 22FDX process certification, provides a 3D fast EM simulation tool integrated in Cadence Virtuoso design flow. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation.

 What’s new in IRIS 2018

  • Support bias table and rho table in IRIS to account for technology variations for advanced IC nodes. 
  • Improve via merge efficiency with 10x speedup for large scale via arrays and make via merge one-time operation to save re-run overhead.
  • Support IRIS export to HFSS 3D Layout with tuned simulation settings to ensure accuracy as part of Xpeedic and Ansys software partnership.
  • Unify IRIS2HFSS and IRIS2HFSS3DLayout flow to simplify IRIS simulation project export usage.
  • Support automated port search and define feature based on pre-defined pin position.
  • Support Synopsys StarRC Interconnect Technology Format (*.itf) and IRIS Technology (*.lyr) conversion.
  • Reduce IRIS simulation options to simplify IRIS usage and give better user experience.

QQ图片20180522111229

Xpeedic 2018

Xpeedic released new EDA 2018 suites

We are excited to announce the release of Xpeedic 2018 EDA software.

In this release, Xpeedic introduces new product Hermes, many new features and enhancements, and most importantly the memory usage of FEM3D dropped 60% without sacrificing computing efficiency. The new release includes all the three product lines: IC design, high speed signal integrity, and high-performance web solution, which further strengthens Xpeedic’s EDA product proposition: fast, accurate and user friendly.

Highlights in EDA 2018.01

New Product – Hermes

143973000002756406_zc_v59_ic2

Hermes2018 is a co-simulation platform for chip, packaging and PCB, and based on the leading FEM3D and Hybrid simulation engine technology. It introduces two efficient simulation processes (Hermes SI and Hermes RF) for high speed and RF applications in this release, which not only satisfies the fast simulation requirements for high-speed SerDes and DDR on the packaging and board level, but also meets the RF/digital hybrid simulation requirements, prompting the evolution of advanced packaging and high-speed signal simulation technology. 

IRIS/iModeler New Feature

143973000002756406_zc_v60_silicon_wafer

IRIS2018 supports the bias table and rho table for advanced technology node, and takes consideration the conductivity and actual metal line width change within different technology. IRIS obtained the GF 22FDX process certification. It supports the auto-addition of the pin, and the efficiency of via defeaturing is increased by 10x.

ViaExpert New Feature

143973000002756406_zc_v60_芯片

ViaExpert2018 is an industry-leading via modeling and simulation tool. It supports remote and distributed simulation that are managed by Xpeedic Distributed Processing Management(XDPM), manual wiring, and Keepout parameterized library and CMF/SMP modules to provide better solutions for design optimization of 56Gbps and higher speed system.


ChannelExpert New Feature

143973000002756406_zc_v59_ic3 (1)

ChannelExpert 2018 is an unique tool for full channel extraction and simulation. It supports automatically extract the crosstalk between multiple boards and multiple channels; supports developed frequency domain and statistical eye diagram simulation to realize full-channel simulation, crosstalk, COM analysis and statistical eye diagram analysis. 

SnpExpert New Feature

143973000002756406_zc_v59_ic

SnpExpert2018 is a widely-adopted S-parameter exploration tool. It integrates all the S-parameter post-processing functions, and supports Python automation, DFE/CTLE auto-optimization, and new addition of 56Gbps and COM compliance.

JobQueue New Feature

143973000002756406_zc_v59_ic4

JobQueue2018 is an industry-leading simulation job management platform with dynamic allocation of computing resource, validity checking, HPC/PBS, and real-time display of simulation results to improve tool usage.

In addition, Xpeedic also releases a complete simulation process for IC design in advanced technology node with the partnership of Ansys HFSS, and XpeedicBridge, an interface module to connect most of the mainstream EDA tools with Xpeedic.

DesignCon2015-Banner

DesignCon 2015

Date: Jan. 28-29, 2015.
Location: Santa Clara.

Xpeedic Technology, Inc. will exhibit at DesignCon 2015 at Santa Clara on Jan. 28-29, 2015.

Xpeedic will showcase their high speed signal integrity (SI) solution and RF front end miniaturization solution in the conference. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications.

Please visit Xpeedic at Booth #912 to find out more.

website: http://www.designcon.com/

DesignCon2014-Banner

Xpeedic to Exhibit at DesignCon 2014

Xpeedic Technology, Inc. will exhibit at DesignCon 2014 at Santa Clara on Jan. 28-31, 2014. Xpeedic will showcase their EDA software and System-in-Package (SiP) design service in the conference.

Xpeedic will bring fast and accurate signal integrity software for IC-package-system designs. ViaExpert enables fast via modeling and simulation for both pre-layout and post-layout scenarios. SnpExpert provides quick way to view S-parameter and the associated TDR. Hermes tool provides signal and power integrity simulation for complex IC-package-board designs including thru-silicon-via (TSV).

Xpeedic’s SiP design service enables customers to achieve system miniaturization by integrating ICs from different process into one package. Their IP on silicon integrated passive devices (IPD) empowers further miniaturization by integrating the peripheral passives for a broad range of RF applications.

Please visit Xpeedic at Booth #755 to find out more.