Xpeedic to Exhibit at SMIC 2019 Technology Symposium

  • Time: September 19, 2019
  • Location: Shanghai

Xpeedic Technology will be exhibiting at the SMIC 2019 Technology Symposium Shanghai on Sept. 19. Featured as in-booth demos will include

  • A Complete EM Simulation Suite for On-Chip Passives in SMIC Advanced Nodes

As Moore’s Law continues scaling and 5G moves to high frequencies including millimeter wave, EM simulation is required to be three dimensional and full-wave, accurate from DC to THz. IRIS is the state-of-the-art EM simulation technology tailored to advanced process nodes.

  • Integrated Passive Device Technology for RF Front End Design

IPD is a core technology to achieve highly integrated RF front-end modules. Utilizing high-resistance silicon and thick copper processes, IPD has both consistency and high integration of semiconductor process, and good RF performance similar to traditional thick film processes such as LTCC. With its unique IPD design methodology and flow, Xpeedic has developed a series of filters, duplexers, couplers, power dividers and other devices, which are ready to be used in antenna switch modules, power amplifier modules and other RF front-end modules.

  • IPD-enabled System-in-Package for Integrated System

SiP technology can integrate multiple chips of different processes (CMOS, SOI, GaAs, etc.) and different functions (digital, analog, RF, etc.) into one package, achieving the advantages of miniaturization, high performance and low cost. Xpeedic can integrate its unique IPD into SiP and achieve even higher integration. Thanks to its differentiating EDA tools, dedicated IPD/SiP design teams, wafer and packaging partners, the company is able to provide customers with one-stop SiP solutions and services.


Xpeedic to Exhibit at FD-SOI Forum and RF-SOI Workshop 2019

  • Date: September 16-17, 2019
  • Place: Shanghai, China

The 7th Shanghai FD-SOI Forum & 2019 International RF-SOI Workshop will be held in Shanghai at September 16-17, 2019.

The 7th Shanghai FD-SOI Forum

This 7th Shanghai FD-SOI Forum will focus on Automotive and IoT applications, products, and supply chain with AI/Edge Computing being discussed in conjunction with Automotive and IoT. There are keynote speeches by executives from Fabless and foundries. The theme of this year’s Forum is Deployment of FD-SOI, for which there are two sessions: AIoT using FD-SOI and automotive electronics using FD-SOI.

Visit here for FD-SOI event.

2019 International RF-SOI Workshop

The RF-SOI Workshop will be focused on 5G connectivity and its opportunity for SOI Industry. Keynote speaker will include 5G carrier, system provider and device maker. They will provide insight on the latest development on 5G deployment and RF-SOI readiness. In the afternoon session, there will be “China RF-SOI Ecosystem” and “RF Value Chain”. It will be focused on RF design and foundry platform for 5G RF-SOI application in China. Also worldwide SOI supply chain will be presented.

Visit here for RF-SOI event.

As an active member of SOI Industry Consortium, Xpeedic has been collaborating with members in the SOI eco-system to provide innovative EDA tools and IP solution to its customers. Xpeedic’s passive modeling and simulation tool, IRIS, has been certified on FD-SOI process nodes including 22FDX from GlobalFoundries and 28FDS from Samsung Foundry. Xpeedic’s IPD/SiP solution helps RF Front End (RFFE) design customers, where RF-SOI is the main technology player, to achieve high integration and system miniaturization.

In 2019 International RF-SOI Workshop, Dr. Feng Ling, CEO of Xpeedic Technology, will give a presentation titled “Innovative EDA Solutions to Enable Differentiated RF-SOI Designs” in the China RF-SOI Ecosystem session to showcase Xpeedic’s contribution.


Xpeedic to Exhibit at WSC2019









EDA Enablement for RF- and FD-SOI

  • SOI论坛
  • 5/18 15:55
  • CEO 凌峰博士


  • EDA/IP设计服务论坛
  • 5/18 16:00
  • 副总裁 代文亮博士



Banner-Xpeedic EDA Seminar4.24

Xpeedic EDA Seminar Series-DesignCon (Taiwan)


一年一度高速設計行業的奧斯卡盛會——DesignCon2019,前不久剛剛在美國落下帷幕。Xpeedic 在大會現場呈現了眾多自主研發、國際最高水準的高速設 計解決方案,並登上代表著全球電子工程領域最高榮譽的 DesignCon 論文論壇, 和全球工程師分享了頂尖的高速連接器等研發技術的最新進展。

在大會進行前後,Xpeedic 收到了非常多工程師夥伴的關注,希望能夠整理 這屆 DesignCon 大會的熱門技術,讓那些無法親臨現場的工程師也能與時俱進。 因此 Xpeedic 特别為大家準備了一場內容豐富、節奏緊湊的研討會, 囊括 DesignCon 最熱門技術和 Xpeedic DesignCon 最受歡迎技術兩大板塊,由 Xpeedic 與 Polar的技術專家面對面與您共用。



  •  IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
  • Quick via modeling and optimization from connector footprint
  • Fast SI/PI simulation of 2.5D interposer with TSV
  • Fast and accurate fiber weave modeling and simulation, and calculate PCB differential pair skew or its effect
  • Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems


  • 時間:2019年4月24日  週三 09:30-15:30
  • 地點:臺北市忠孝東路三段1號 ( 集思北科大會議中心 2 樓貝塔廳 201 會議室-億光大樓 )
  • 適用對象:從事高速設計、信號完整性分析領域
  • 報名熱線:(02)2991-7470, Ext:14 蕭小姐


  • 9:30-10:00 簽到
  • 10:00-10:45 2019 DesignCon 熱門技術總覽
  • 10:45-11:00 Tea Time
  • 11:00-11:45 Xpeedic DesignCon 最受歡迎技術之一: IEEE P370 de-embedding and quality check for S-parameter
  • 12:00-13:00 午餐時間
  • 13:00-14:00 Xpeedic DesignCon 最受歡迎技術之二: Fast crosstalk scan for vias and channels
  • 14:00-14:15 Tea Time
  • 14:15-15:00 Xpeedic DesignCon 最受歡迎技術之三: Skew evaluation for PCB differential pair and connector
  • 15:00-15:30 Q&A



CDNLive Silicon Valley 2019

Date: April 2-3, 2019
Location: Santa Clara Convention Center – Santa Clara, CA

CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems that transform the way people live, work, and play.

As Cadence Connections program member, Xpeedic will demonstrate its latest EDA solutions at Designer Expo and will present the following technical paper.

Title: Enabling Pin Field Crosstalk Scan for High-Speed Designs

Author: Feng Ling, Xpeedic, Kevin Cai and Bidyut Sen, Cisco

Time: 9:30AM-10:10AM, April 2

Agenda at a Glance

TimeDay One
Tuesday - April 2
Day Two
Wednesday - April 3
8:00am-9:30amBreakfast / RegistrationBreakfast / Registration
9:30am-10:10amBreakout SessionsBreakout Sessions
10:30am-12:00pmKeynotesBreakout Sessions
12:00pm-1:30pmLunch / Designer ExpoLunch / Designer Expo
1:30pm-5:00pmBreakout SessionsBreakout Sessions
5:00pm-6:30pmReception / Designer ExpoClosing Reception / Best Presentation Awards

Click here to get more details and register.

Banner-IPC PCB

IPC PCB Design Forum

Date: March 20, 2019

Location: Booth 3300, Hall C3, Shanghai New International Expo Center

Xpeedic will present at IPC PCB Design Forum with the topic titled < Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff >.

Please click here to find the detail agenda and register.

Banner-Xpeedic EDA Seminar3.21

Xpeedic EDA Seminar Series-DesignCon




  • IEEE P370 compatible de-embedding and qualitycheck for measured S-parameters up to 50GHz
  • Quick via modeling and optimization fromconnector footprint
  • Fast SI/PI simulation of 2.5D interposer withTSV
  • Fast and accurate fiber weave modeling and simulation, and calculate PCB differential pair skew or its effect
  • Automated crosstalk scan, impedance scan andDRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis anddesign margin evaluation for high speed backplane systems
  • ……


  • 时间:2019年3月21日 周四10:00-16:00
  • 地点:祖冲之路2290弄展想广场1号楼1101室(近2号线广兰路站)
  • 适用对象:从事高速设计、信号完整性分析的工程师


  • 9:30~10:00 签到
  • 10:00~10:45 2019 DesignCon 热门技术纵览
  • 10:45~11:30 芯禾科技DesignCon最受欢迎技术之一: IEEE P370 de-embedding and quality check forS-parameter
  • 12:00~13:30 午餐
  • 13:30~14:15 芯禾科技DesignCon最受欢迎技术之二: Fast crosstalk scan for vias and channels
  • 14:15~15:00 芯禾科技DesignCon最受欢迎技术之三: Skew evaluation for PCB differential pair andconnector
  • 15:00~15:15 茶歇
  • 15:15~16:00 互动问答





Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff

Crosstalk analysis for high speed PCB design becomes more and more important due to the high data rate and tightly coupled routing. Traditional circuit-based analysis can not meet the accuracy demand. Three-dimensional (3D) full-wave electromagnetic solver is required to capture the complex 3D PCB environment and the frequency-dependent phenomena. This paper introduces a novel hybrid solver technology with both speed and accuracy. Crosstalk metrics to quantify the crosstalk level are also developed by post-processing S-parameter. Combining these two techniques allows designer to achieve full board crosstalk in a few hours as planned, which significantly reduces the post-layout check time and ensure timely sign-off.

Please click the link below to download the file.(Please make sure you login first)


Fast and Accurate Fiber Weave Modeling and Simulation

As the data rate of SerDes channel increases from 25Gbps to 56Gbps and 112Gbps, the requirement for timing skew of differential signals is becoming tighter and tighter. The skew of differential pairs can be introduced by the unbalanced differential trace routing on glass weaves. In high-speed PCB designs, there are many possible combinations considering different glass weave patterns and different trace routings, which makes quantifying the impact of glass weave on skew a challenging task. It requires electromagnetic simulation tool vendor to come up with the design guideline for PCB engineers.

Please click the link below to download the file.(Please make sure you login first)


Accurate Dk/Df Extraction for High-speed SI Applications

This application note presents an accurate way to perform dielectric constant (Dk) and dielectric loss (Df) extraction over a wide range of laminate materials for high-speed SI applications. The Through-Only De-embedding (TOD) method with optimization is used for this Dk/Df extraction. The resultant frequency dependent material models is ready to be used in electromagnetic simulation tools in market.

Please click the link below to download the file.(Please make sure you login first)