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Xpeedic to Exhibit at WSC2019

日期:2019年5月17-19日
地点:南京,国际博览会议中心
展位号:E1

2019世界半导体大会暨第十七届中国半导体市场年会即将于5月17-19日在南京国际博览会议中心开幕。

本届大会以创新协作、世界同“芯”为主题,全方位展示半导体产业的发展动态和最新成果,促进积极有效的交流合作;大会将采用“2+N+1”的举办模式,举办2场主论坛(高峰论坛和创新峰会),N场专题论坛/专题活动以及1场专业展会;大会还将公布“第十三届(2018年度)中国半导体创新产品和技术项目”,发布《世界半导体市场趋势展望白皮书》、《中国半导体产业发展状况白皮书》等相关评选结果与专题报告。

芯禾科技在本届大会上将主要展示其EDA/IP整合解决方案的最新研发成果,包括EDA设计仿真工具、无线射频IPD集成无源器件和SiP系统级封装服务的三大产品线。

WSC2019-2

WSC2019-1

现场演讲:

大会期间,芯禾科技还将在本次大会上带来两篇论坛演讲,分别是

EDA Enablement for RF- and FD-SOI

  • SOI论坛
  • 5/18 15:55
  • CEO 凌峰博士

《仿真驱动EDA解决方案助力先进IC-封装-系统设计》

  • EDA/IP设计服务论坛
  • 5/18 16:00
  • 副总裁 代文亮博士

大会的详细日程安排如下:

日程表
扫描二维码报名参会
报名二维码

Samsung Foundry Forum 2019 US

Date: May 14, 2019, 1pm-7pm

Place: Santa Clara Marriott, Santa Clara, CA


As Samsung Advanced Foundry Ecosystem (SAFE™) partner, Xpeedic will be exhibiting at Samsung Foundry Forum at the Santa Clara Marriott, Santa Clara, CA on May 14, 2019.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool

Certified on Samsung’s advanced process nodes including its FD-SOI 28FDS and 14nm FinFET node

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

SFF2019-1

See the event details here.

Xpeedic EDA Seminar Series-DesignCon (Taiwan)

親愛的客戶您好,

一年一度高速設計行業的奧斯卡盛會——DesignCon2019,前不久剛剛在美國落下帷幕。Xpeedic 在大會現場呈現了眾多自主研發、國際最高水準的高速設 計解決方案,並登上代表著全球電子工程領域最高榮譽的 DesignCon 論文論壇, 和全球工程師分享了頂尖的高速連接器等研發技術的最新進展。

在大會進行前後,Xpeedic 收到了非常多工程師夥伴的關注,希望能夠整理 這屆 DesignCon 大會的熱門技術,讓那些無法親臨現場的工程師也能與時俱進。 因此 Xpeedic 特别為大家準備了一場內容豐富、節奏緊湊的研討會, 囊括 DesignCon 最熱門技術和 Xpeedic DesignCon 最受歡迎技術兩大板塊,由 Xpeedic 與 Polar的技術專家面對面與您共用。

機會難得,歡迎大家踴躍報名!

DesignCon热门技术

  •  IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
  • Quick via modeling and optimization from connector footprint
  • Fast SI/PI simulation of 2.5D interposer with TSV
  • Fast and accurate fiber weave modeling and simulation, and calculate PCB differential pair skew or its effect
  • Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems

研討會安排

  • 時間:2019年4月24日  週三 09:30-15:30
  • 地點:臺北市忠孝東路三段1號 ( 集思北科大會議中心 2 樓貝塔廳 201 會議室-億光大樓 )
  • 適用對象:從事高速設計、信號完整性分析領域
  • 報名熱線:(02)2991-7470, Ext:14 蕭小姐 sandy.hsiao@polarinstruments.asia

研討會议程

  • 9:30-10:00 簽到
  • 10:00-10:45 2019 DesignCon 熱門技術總覽
  • 10:45-11:00 Tea Time
  • 11:00-11:45 Xpeedic DesignCon 最受歡迎技術之一: IEEE P370 de-embedding and quality check for S-parameter
  • 12:00-13:00 午餐時間
  • 13:00-14:00 Xpeedic DesignCon 最受歡迎技術之二: Fast crosstalk scan for vias and channels
  • 14:00-14:15 Tea Time
  • 14:15-15:00 Xpeedic DesignCon 最受歡迎技術之三: Skew evaluation for PCB differential pair and connector
  • 15:00-15:30 Q&A

發送“姓名+公司名稱+職位+手機號碼”至郵箱 sandy.hsiao@polarinstruments.asia,馬上報名!

CDNLive Silicon Valley 2019

Date: April 2-3, 2019
Location: Santa Clara Convention Center – Santa Clara, CA

CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems that transform the way people live, work, and play.

As Cadence Connections program member, Xpeedic will demonstrate its latest EDA solutions at Designer Expo and will present the following technical paper.

Title: Enabling Pin Field Crosstalk Scan for High-Speed Designs

Author: Feng Ling, Xpeedic, Kevin Cai and Bidyut Sen, Cisco

Time: 9:30AM-10:10AM, April 2

Agenda at a Glance

TimeDay One
Tuesday - April 2
Day Two
Wednesday - April 3
8:00am-9:30amBreakfast / RegistrationBreakfast / Registration
9:30am-10:10amBreakout SessionsBreakout Sessions
10:30am-12:00pmKeynotesBreakout Sessions
12:00pm-1:30pmLunch / Designer ExpoLunch / Designer Expo
1:30pm-5:00pmBreakout SessionsBreakout Sessions
5:00pm-6:30pmReception / Designer ExpoClosing Reception / Best Presentation Awards

Click here to get more details and register.

Xpeedic to Exhibit at DAC2019

Date: June 2-6, 2019

Place: Las Vegas, NV, US

Booth#:622

Xpeedic Technology will showcase its latest solutions at the 2019 Design Automation Conference (DAC) in Las Vegas, June 2-6.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

dac-5g

5G RFIC in Advanced Process Nodes
  • IRIS,Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver, certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

IC-Package Co-design for 5G Application
  • Metis,IC-package co-simulation tool to enable 5G system-in-package designs, and supports advanced packaging technologies for CPU, GPU, network processor, FPGA designs to enable artificial intelligence applications in 5G era.

Integrated Passive Devices for 5G NR
  • RF front end module has become more and more complicated with mobile technology evolving from 2G, 3G, 4G to 5G. Increasing number of bands, carrier aggregation, and MIMO demand more filters and more integration in RF front end. Integrated passive devices (IPD) provide great advantages of miniaturization, high consistency, low cost and high integration over discrete. Xpeedic has partnered with industry leading IPD foundries with both silicon and glass substrates. With the extensive IPD design experience,Xpeedic helps customers to choose the right technology to meet their spec.

More details to see here.

Xpeedic to Exhibit at IMS2019

Date: June 2-7, 2019

Place: Boston, US

Booth#: 210


Xpeedic Technology will showcase its latest solutions at the 2019 IEEE MTT-S International Microwave Symposium (IMS) in Boston Convention & Exhibition Center, June 2-7.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver

Certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

  • IPD for RF FE module design

Advanced IPD technology to enable passive integration for RF front end, helping customers to achieve faster design convergence from spec to volume production.

  • Through Glass Via (TGV) solution in collaboration with Corning

Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. A diplexer built with TGV shows less in-band insertion loss and greater out-of-band rejection yet still compact size.


Xpeedic will also present at IMS MicroApps Theatre

* Title: Integrated Passive Devices (IPD) for RF Front End Integration (WEMA35)

* Time: June 5, 12:30-12:45

See the event details here.

IMS2019-2

IPC PCB Design Forum

Date: March 20, 2019

Location: Booth 3300, Hall C3, Shanghai New International Expo Center

Xpeedic will present at IPC PCB Design Forum with the topic titled < Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff >.

Please click here to find the detail agenda and register.

Xpeedic EDA Seminar Series-DesignCon

尊敬的工程师伙伴,
一年一度高速设计行业的奥斯卡盛会——DesignCon2019,前不久刚刚在美国落下帷幕。芯禾科技作为参展的最大的国内EDA公司,在大会现场呈现了众多自主研发、国际最高水平的高速设计解决方案,并登上代表着全球电子工程领域最高荣誉的DesignCon论文论坛,和全球工程师分享了顶尖的高速连接器等研发技术的最新进展。

      在大会进行前后,我们收到了非常多工程师伙伴的关注,希望我们能够整理这届DesignCon大会的热门技术,带回国内让那些无法亲临现场的工程师也能与时俱进。现在,是我们兑现这个承诺的时候了。芯禾科技为大家准备了一场内容丰富、节奏紧凑的研讨会,囊括DesignCon最热门技术和芯禾科技DesignCon最受欢迎技术两大板块,由芯禾科技的技术专家面对面与您共享。
      机会难得,欢迎大家报名抢票!

DesignCon热门技术

  • IEEE P370 compatible de-embedding and qualitycheck for measured S-parameters up to 50GHz
  • Quick via modeling and optimization fromconnector footprint
  • Fast SI/PI simulation of 2.5D interposer withTSV
  • Fast and accurate fiber weave modeling and simulation, and calculate PCB differential pair skew or its effect
  • Automated crosstalk scan, impedance scan andDRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis anddesign margin evaluation for high speed backplane systems
  • ……

研讨会安排

  • 时间:2019年3月21日 周四10:00-16:00
  • 地点:祖冲之路2290弄展想广场1号楼1101室(近2号线广兰路站)
  • 适用对象:从事高速设计、信号完整性分析的工程师

研讨会议程

  • 9:30~10:00 签到
  • 10:00~10:45 2019 DesignCon 热门技术纵览
  • 10:45~11:30 芯禾科技DesignCon最受欢迎技术之一: IEEE P370 de-embedding and quality check forS-parameter
  • 12:00~13:30 午餐
  • 13:30~14:15 芯禾科技DesignCon最受欢迎技术之二: Fast crosstalk scan for vias and channels
  • 14:15~15:00 芯禾科技DesignCon最受欢迎技术之三: Skew evaluation for PCB differential pair andconnector
  • 15:00~15:15 茶歇
  • 15:15~16:00 互动问答

点击下面图标,开启你的研讨会之旅:

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