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Xpeedic to Exhibit at WSC2019

日期:2019年5月17-19日
地点:南京,国际博览会议中心
展位号:E1

2019世界半导体大会暨第十七届中国半导体市场年会即将于5月17-19日在南京国际博览会议中心开幕。

本届大会以创新协作、世界同“芯”为主题,全方位展示半导体产业的发展动态和最新成果,促进积极有效的交流合作;大会将采用“2+N+1”的举办模式,举办2场主论坛(高峰论坛和创新峰会),N场专题论坛/专题活动以及1场专业展会;大会还将公布“第十三届(2018年度)中国半导体创新产品和技术项目”,发布《世界半导体市场趋势展望白皮书》、《中国半导体产业发展状况白皮书》等相关评选结果与专题报告。

芯禾科技在本届大会上将主要展示其EDA/IP整合解决方案的最新研发成果,包括EDA设计仿真工具、无线射频IPD集成无源器件和SiP系统级封装服务的三大产品线。

WSC2019-2

WSC2019-1

现场演讲:

大会期间,芯禾科技还将在本次大会上带来两篇论坛演讲,分别是

EDA Enablement for RF- and FD-SOI

  • SOI论坛
  • 5/18 15:55
  • CEO 凌峰博士

《仿真驱动EDA解决方案助力先进IC-封装-系统设计》

  • EDA/IP设计服务论坛
  • 5/18 16:00
  • 副总裁 代文亮博士

大会的详细日程安排如下:

日程表
扫描二维码报名参会
报名二维码

Samsung Foundry Forum 2019 US

Date: May 14, 2019, 1pm-7pm

Place: Santa Clara Marriott, Santa Clara, CA


As Samsung Advanced Foundry Ecosystem (SAFE™) partner, Xpeedic will be exhibiting at Samsung Foundry Forum at the Santa Clara Marriott, Santa Clara, CA on May 14, 2019.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool

Certified on Samsung’s advanced process nodes including its FD-SOI 28FDS and 14nm FinFET node

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

SFF2019-1

See the event details here.

CDNLive Silicon Valley 2019

Date: April 2-3, 2019
Location: Santa Clara Convention Center – Santa Clara, CA

CDNLive Silicon Valley brings together Cadence® technology users, developers, and industry experts for networking, sharing best practices on critical design and verification issues, and discovering new techniques for designing advanced silicon, SoCs, and systems that transform the way people live, work, and play.

As Cadence Connections program member, Xpeedic will demonstrate its latest EDA solutions at Designer Expo and will present the following technical paper.

Title: Enabling Pin Field Crosstalk Scan for High-Speed Designs

Author: Feng Ling, Xpeedic, Kevin Cai and Bidyut Sen, Cisco

Time: 9:30AM-10:10AM, April 2

Agenda at a Glance

TimeDay One
Tuesday - April 2
Day Two
Wednesday - April 3
8:00am-9:30amBreakfast / RegistrationBreakfast / Registration
9:30am-10:10amBreakout SessionsBreakout Sessions
10:30am-12:00pmKeynotesBreakout Sessions
12:00pm-1:30pmLunch / Designer ExpoLunch / Designer Expo
1:30pm-5:00pmBreakout SessionsBreakout Sessions
5:00pm-6:30pmReception / Designer ExpoClosing Reception / Best Presentation Awards

Click here to get more details and register.

Xpeedic to Exhibit at DAC2019

Date: June 2-6, 2019

Place: Las Vegas, NV, US

Booth#:622

Xpeedic Technology will showcase its latest solutions at the 2019 Design Automation Conference (DAC) in Las Vegas, June 2-6.

Xpeedic 5G solution enables designers inSoC, RFIC, packaging, board to build better 5G systems with theirdifferentiating technologies. It includes the following highlights:

dac-5g

5G RFIC in Advanced Process Nodes
  • IRIS,Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver, certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

IC-Package Co-design for 5G Application
  • Metis,IC-package co-simulation tool to enable 5G system-in-package designs, and supports advanced packaging technologies for CPU, GPU, network processor, FPGA designs to enable artificial intelligence applications in 5G era.

Integrated Passive Devices for 5G NR
  • RF front end module has become more and more complicated with mobile technology evolving from 2G, 3G, 4G to 5G. Increasing number of bands, carrier aggregation, and MIMO demand more filters and more integration in RF front end. Integrated passive devices (IPD) provide great advantages of miniaturization, high consistency, low cost and high integration over discrete. Xpeedic has partnered with industry leading IPD foundries with both silicon and glass substrates. With the extensive IPD design experience,Xpeedic helps customers to choose the right technology to meet their spec.

More details to see here.

Xpeedic to Exhibit at IMS2019

Date: June 2-7, 2019

Place: Boston, US

Booth#: 210


Xpeedic Technology will showcase its latest solutions at the 2019 IEEE MTT-S International Microwave Symposium (IMS) in Boston Convention & Exhibition Center, June 2-7.

Featured as in-booth demos will include

  • IRIS, Virtuoso-integrated EM simulation tool with the state-of-the-art 3D planar solver

Certified on multiple foundries’ advanced process nodes and proven on RF IC designs including 5G mmWave.

  • Metis, IC-package co-simulation tool

IC-package co-simulation tool to enable system-in-package designs. It also supports advanced packaging technologies such as 2.5D interposer with TSV.

  • IPD for RF FE module design

Advanced IPD technology to enable passive integration for RF front end, helping customers to achieve faster design convergence from spec to volume production.

  • Through Glass Via (TGV) solution in collaboration with Corning

Through Glass Via technology has become a promising technology candidate to realize integrated, low cost and high performance passive devices. A diplexer built with TGV shows less in-band insertion loss and greater out-of-band rejection yet still compact size.


Xpeedic will also present at IMS MicroApps Theatre

* Title: Integrated Passive Devices (IPD) for RF Front End Integration (WEMA35)

* Time: June 5, 12:30-12:45

See the event details here.

IMS2019-2

IPC PCB Design Forum

Date: March 20, 2019

Location: Booth 3300, Hall C3, Shanghai New International Expo Center

Xpeedic will present at IPC PCB Design Forum with the topic titled < Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff >.

Please click here to find the detail agenda and register.

MWC 2019

一年一度的 MWC 世界移动通信展会2/25-2/28在巴塞罗那如火如荼的举行。这期间,各大厂商们“蓄谋已久”的年度大招频出,这些技术将对如今越来越同质化的手机通信市场带来耳目一新的新鲜元素,并引领整个行业革新和创新趋势。微信图片_20190227101147

特殊玻璃行业的全球领导厂商康宁公司联合芯禾科技,在本次大会上发布了针对5G射频前端模组和Wifi应用的玻璃通孔(ThroughGlass Vias, TGV)解决方案。

微信图片_20190227101153

当前移动和物联网设备市场正经历着爆发式的增长。尽管数字电路在摩尔定律的驱动下继续增加着集成度,但射频电路却无法按相同比例减小尺寸。因此射频电路尤其是无源器件部分的进一步集成,成为系统小型化的关键。

为了满足不断增长的小型化需求,在增加功能的同时减小尺寸、降低成本,集成无源器件(IPD)技术已成为射频前端设计的一种令人期待的先进技术,它也已经从低温共烧陶瓷(LTCC)发展到薄膜技术,如使用高阻硅(HRSi)或玻璃基板。在最新的研发进程中,玻璃通孔技术已被视为实现集成、低成本和高性能无源器件最有前途的技术之一。

微信图片_20190227101158

芯禾科技的TGV解决方案具有多项显著优势:与二维平面电感相比,采用TGV结构的三维电感具有更好的品质因数;与硅相比,玻璃的介电常数较低,电阻率较高,因而具有较好的高频性能;诸如使用TGV构建的滤波器和双工器之类的无源器件,在确保较小的带内插损和较大的带外抑制能力的同时,还能在尺寸上做小。

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如果您在MWC现场,我们非常欢迎您至康宁公司展位(Hall 2 Executive Meeting Rooms, Upper Level, Room #2G9Ex)了解详情

Xpeedic’s IRIS Qualified on GLOBALFOUNDRIES 12LP Process for High-Performance Applications

Cupertino, CA. — Feb 20, 2019 —Xpeedic Technology, Inc. today announced that its 3D full-wave electromagnetic (EM) simulation tool, IRIS, has been qualified on GLOBALFOUNDRIES’ 12nm Leading-Performance (12LP) process technology. This qualification enables designers to run IRIS with confidence using the certified IRIS process file available on GF’s 12LP FinFET semiconductor manufacturing process.

GF’s 12LP technology provides as much as a 10 percent improvement in logic circuit density and more than a 15 percent improvement in performance over 14nm FinFET solutions, satisfying the processing needs of the most demanding compute-intensive applications from artificial intelligence and virtual reality to high-end smartphones and networking infrastructure.

“Accurate EM simulation tools are critical for successful first design pass for our clients’ compute-intensive applications,” said Richard Trihy, vice president, Design Enablement at GF. “The qualification of Xpeedic’s EM tool provides designers predictable EM simulation results for advanced process technologies.”

“We are very pleased that IRIS is able to achieve excellent correlation with measurement and thus qualified for GF’s 12LP process,” said Dr. Feng Ling, CEO of Xpeedic Technology, “As GF FDXcelerator and RFwave member, Xpeedic will continue the collaboration with GF on various process technologies to help our mutual clients with innovative solutions and services.”

The electromagnetic qualification program by GF ensures that every EM tool qualified by the program meets GF’s highest quality standards. With this qualification, IC designers can choose their preferred EM simulation tool, and its corresponding process file, to ensure their design confidence and reduce time-to-market.