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Xpeedic EDA Seminar Series-DesignCon (Taiwan)

親愛的客戶您好,

一年一度高速設計行業的奧斯卡盛會——DesignCon2019,前不久剛剛在美國落下帷幕。Xpeedic 在大會現場呈現了眾多自主研發、國際最高水準的高速設 計解決方案,並登上代表著全球電子工程領域最高榮譽的 DesignCon 論文論壇, 和全球工程師分享了頂尖的高速連接器等研發技術的最新進展。

在大會進行前後,Xpeedic 收到了非常多工程師夥伴的關注,希望能夠整理 這屆 DesignCon 大會的熱門技術,讓那些無法親臨現場的工程師也能與時俱進。 因此 Xpeedic 特别為大家準備了一場內容豐富、節奏緊湊的研討會, 囊括 DesignCon 最熱門技術和 Xpeedic DesignCon 最受歡迎技術兩大板塊,由 Xpeedic 與 Polar的技術專家面對面與您共用。

機會難得,歡迎大家踴躍報名!

DesignCon热门技术

  •  IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
  • Quick via modeling and optimization from connector footprint
  • Fast SI/PI simulation of 2.5D interposer with TSV
  • Fast and accurate fiber weave modeling and simulation, and calculate PCB differential pair skew or its effect
  • Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems

研討會安排

  • 時間:2019年4月24日  週三 09:30-15:30
  • 地點:臺北市忠孝東路三段1號 ( 集思北科大會議中心 2 樓貝塔廳 201 會議室-億光大樓 )
  • 適用對象:從事高速設計、信號完整性分析領域
  • 報名熱線:(02)2991-7470, Ext:14 蕭小姐 sandy.hsiao@polarinstruments.asia

研討會议程

  • 9:30-10:00 簽到
  • 10:00-10:45 2019 DesignCon 熱門技術總覽
  • 10:45-11:00 Tea Time
  • 11:00-11:45 Xpeedic DesignCon 最受歡迎技術之一: IEEE P370 de-embedding and quality check for S-parameter
  • 12:00-13:00 午餐時間
  • 13:00-14:00 Xpeedic DesignCon 最受歡迎技術之二: Fast crosstalk scan for vias and channels
  • 14:00-14:15 Tea Time
  • 14:15-15:00 Xpeedic DesignCon 最受歡迎技術之三: Skew evaluation for PCB differential pair and connector
  • 15:00-15:30 Q&A

發送“姓名+公司名稱+職位+手機號碼”至郵箱 sandy.hsiao@polarinstruments.asia,馬上報名!

Xpeedic EDA Seminar Series-DesignCon

尊敬的工程师伙伴,
一年一度高速设计行业的奥斯卡盛会——DesignCon2019,前不久刚刚在美国落下帷幕。芯禾科技作为参展的最大的国内EDA公司,在大会现场呈现了众多自主研发、国际最高水平的高速设计解决方案,并登上代表着全球电子工程领域最高荣誉的DesignCon论文论坛,和全球工程师分享了顶尖的高速连接器等研发技术的最新进展。

      在大会进行前后,我们收到了非常多工程师伙伴的关注,希望我们能够整理这届DesignCon大会的热门技术,带回国内让那些无法亲临现场的工程师也能与时俱进。现在,是我们兑现这个承诺的时候了。芯禾科技为大家准备了一场内容丰富、节奏紧凑的研讨会,囊括DesignCon最热门技术和芯禾科技DesignCon最受欢迎技术两大板块,由芯禾科技的技术专家面对面与您共享。
      机会难得,欢迎大家报名抢票!

DesignCon热门技术

  • IEEE P370 compatible de-embedding and qualitycheck for measured S-parameters up to 50GHz
  • Quick via modeling and optimization fromconnector footprint
  • Fast SI/PI simulation of 2.5D interposer withTSV
  • Fast and accurate fiber weave modeling and simulation, and calculate PCB differential pair skew or its effect
  • Automated crosstalk scan, impedance scan andDRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis anddesign margin evaluation for high speed backplane systems
  • ……

研讨会安排

  • 时间:2019年3月21日 周四10:00-16:00
  • 地点:祖冲之路2290弄展想广场1号楼1101室(近2号线广兰路站)
  • 适用对象:从事高速设计、信号完整性分析的工程师

研讨会议程

  • 9:30~10:00 签到
  • 10:00~10:45 2019 DesignCon 热门技术纵览
  • 10:45~11:30 芯禾科技DesignCon最受欢迎技术之一: IEEE P370 de-embedding and quality check forS-parameter
  • 12:00~13:30 午餐
  • 13:30~14:15 芯禾科技DesignCon最受欢迎技术之二: Fast crosstalk scan for vias and channels
  • 14:15~15:00 芯禾科技DesignCon最受欢迎技术之三: Skew evaluation for PCB differential pair andconnector
  • 15:00~15:15 茶歇
  • 15:15~16:00 互动问答

点击下面图标,开启你的研讨会之旅:

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Automated Crosstalk Scan, Impedance Scan and DRC+ for Signal Integrity Signoff

Crosstalk analysis for high speed PCB design becomes more and more important due to the high data rate and tightly coupled routing. Traditional circuit-based analysis can not meet the accuracy demand. Three-dimensional (3D) full-wave electromagnetic solver is required to capture the complex 3D PCB environment and the frequency-dependent phenomena. This paper introduces a novel hybrid solver technology with both speed and accuracy. Crosstalk metrics to quantify the crosstalk level are also developed by post-processing S-parameter. Combining these two techniques allows designer to achieve full board crosstalk in a few hours as planned, which significantly reduces the post-layout check time and ensure timely sign-off.

Please click the link below to download the file.

Fast and Accurate Fiber Weave Modeling and Simulation

As the data rate of SerDes channel increases from 25Gbps to 56Gbps and 112Gbps, the requirement for timing skew of differential signals is becoming tighter and tighter. The skew of differential pairs can be introduced by the unbalanced differential trace routing on glass weaves. In high-speed PCB designs, there are many possible combinations considering different glass weave patterns and different trace routings, which makes quantifying the impact of glass weave on skew a challenging task. It requires electromagnetic simulation tool vendor to come up with the design guideline for PCB engineers.

Please click the link below to download the file.

Accurate Dk/Df Extraction for High-speed SI Applications

This application note presents an accurate way to perform dielectric constant (Dk) and dielectric loss (Df) extraction over a wide range of laminate materials for high-speed SI applications. The Through-Only De-embedding (TOD) method with optimization is used for this Dk/Df extraction. The resultant frequency dependent material models is ready to be used in electromagnetic simulation tools in market.

Please click the link below to download the file.

IEEE P370 Compatible De-embedding and Quality Check for Measured S-parameters up to 50Ghz

This application note presents an IEEE P370 compatible and competitive de-embedding and quality check method for measured S-parameters up to 50Ghz in SnpExpert, which gives SI engineers a fast and easy way to post-process and assess S-parameters.

Please click the link below to download the file.

Xpeedic SI Live Demo at DesignCon2019

Hi all,

We are very glad to announce Xpeedic’s high-speed signal integrity live demo series at DesignCon 2019.

The demos will focus on eight hottest topics, and will be presented by industry experts at Xpeedic booth. You will also get chance to receive the new year gifts from Xpeedic.

Signal Integrity Demo Highlights

  • IEEE P370 compatible de-embedding and quality check for measured S-parameters up to 50GHz
  • Through-Only De-embedding (TOD) and optimization based Dk/Df extraction for high-speed and wideband applications
  • Quick via modeling and optimization from connector footprint
  • Fast SI/PI simulation of 2.5D interposer with TSV
  • Fast and accurate fiber weave modeling and simulation
  • Automated crosstalk scan, impedance scan and DRC+ for signal integrity signoff
  • Automated full channel crosstalk analysis and design margin evaluation for high speed backplane systems
  • Web-based passive model management for SI/PI engineers

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MEET US AT

DesignCon2019   |    Booth 525

Select topics and join us!

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Xpeedic to Exhibit at DesignCon 2019

Date: Jan.29-31, 2019

Location: Santa Clara, CA

Booth#: 525

Xpeedic Technology, Inc. will exhibit at DesignCon 2019 at Santa Clara on Jan.29-31, 2019.

DesignCon is the premier conference for chip, board and systems design engineers in the high speed communications and semiconductor communities. The DesignCon Expo Hall offers the latest products and technologies in signal integrity and high-speed design for your current and future projects. You can test and compare emerging tools and technologies from top tier vendors.

At Booth 525, Xpeedic will showcase their latest update in RF front end miniaturization solution and high speed signal integrity (SI) solution in the conference. Their IP on silicon integrated passive devices (IPD) delivers the industry-leading combination of performance and integration to enable system-in-package (SiP) for a broad range of applications. Their fast and accurate SI software enables the quick way to simulate the high speed channel for both pre-layout and post-layout scenarios.

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Register now and use our promo code SPECIAL for a free Expo Pass &20% off any conference Pass!

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Fast Full Board Crosstalk Scan for Signal Integrity Sign-Off for High Speed PCB Designs

Abstract—Crosstalk analysis for high speed PCB design becomes more and more important due to the high data rate and tightly coupled routing. Traditional circuit-based analysis can not meet the accuracy demand. Three-dimensional (3D) full-wave electromagnetic solver is required to capture the complex 3D PCB environment and the frequency-dependent phenomena. However it is prohibitively expensive to simulate the practical large board cases and the resultant tabulated S-parameter cannot be directly used to quantify the crosstalk level. This paper introduces a novel hybrid solver techniques with improved speed and accuracy. The new crosstalk metrics to quantify the crosstalk level are also developed by post-processing S-parameter. Combining these two techniques allows designers to achieve full board crosstalk in a few hours as planned intended with using the tool, which significantly reduces the post-layout review time, allows layout optimization and ensures a timely sign-off.

Please click the link below to download the file.