In high frequency silicon circuit design, passive devices, interconnect, and their mutual coupling have to be taken into account via electromagnetic (EM) simulation. Full-wave EM simulation is becoming necessary to cover the RF frequency of interest including multiple harmonics compared to quasi-static RC extraction. Cadence Virtuoso based schematic and layout flow is widely adopted for IC designers. However, lack of the built-in full-wave EM simulation tool leads to frequent transfer of the layout data between Virtuoso environment and outside EM tools, which is very manual and error-prone. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation. This design flow will greatly help IC designers to reduce the design cycles and achieve first-pass silicon success.
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