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IRIS: Fast EM Simulation with Virtuoso Integration

In high frequency silicon circuit design, passive devices, interconnect, and their mutual coupling have to be taken into account via electromagnetic (EM) simulation. Full-wave EM simulation is becoming necessary to cover the RF frequency of interest including multiple harmonics compared to quasi-static RC extraction. Cadence Virtuoso based schematic and layout flow is widely adopted for IC designers. However, lack of the built-in full-wave EM simulation tool leads to frequent transfer of the layout data between Virtuoso environment and outside EM tools, which is very manual and error-prone. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation. This design flow will greatly help IC designers to reduce the design cycles and achieve first-pass silicon success.

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ViaExpert: 3D Via Modeling and Simulation

Impedance discontinuity in the signal path has a significant impact on signal integrity for high speed channel design. Among the many discontinuities, via discontinuity is the critical one which requires extra attention in channel design. Three-dimensional full-wave EM simulation is constantly used to analyze via discontinuity. Conventional 3D full-wave simulation approach suffers from various drawbacks including the complex model creation and the long simulation time. ViaExpert provides a fast and accurate way to simulate via structures for both pre-layout and post-layout scenarios. For pre-layout analysis, various built-in templates allow users to quickly assemble the models, analyze and optimize SMA, SMD, AC Cap, via array and BGA physical parameters based on design constrains. The model can also be built by extracting the area of interest from the existing layout. The fast 3D FEM and hybrid solver yields accurate results with unprecedented speed. Optimal 3D mesh improves the simulation accuracy and speed. The powerful parameterization on the critical via variables such as antipad size, trace escape layer, and backdrill layer enables quick what-if analysis. Additional features such as exporting to HFSS and CST are also provided for quick benchmarking.

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JobQueue: Simulation Job Management Platform

JobQueue is a web based platform to submit, monitor and manage your simulation jobs, including IRIS, HFSS and so on. As a web application, JobQueue utilizes both client hardware devices and servers based on Client/Server mode, so it’s quite easy to deploy, and get your team to work across the region with only one deployment. JobQueue is quite easy to use, anyone with IE browsing experience can pick up soon. In JobQueue, all heavy computational simulation jobs will dispatch automatically to computing machines’ cluster in order to maximize hardware resource utilization, and make the best of parallel computing and distributed computing. JobQueue built-in queuing and batch simulation system help customer adjust task priority, manage computing resource, save GUI license and increase simulation tool’s utilization ratio. Project management module will supervise and manage submitted tasks for easy back trace and reuse, which greatly increase value to the business enterprise knowledge backlogs. Simulation results real time display forward to browser will definitely improve simulation productivity.

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TmlExpert: Tml Modeling and Simulation

TmlExpert is a fast and accurate Tml modeling and simulation tool.

Transmission lines are key building components which plays an important role in signal integrity. As data rate increases to high Gbps speed, accurate modeling of transmission lines including wideband dielectric model, conductor surface roughness, and solder mask layer is becoming necessity. Calculating impedance with 2D RLGC solver is commonly used for impedance control purpose. Given the length of the transmission line, the S-parameter, TDR, delay, and resultant eye-diagram with bit stream input are often needed. In high speed PCB layout, serpentine traces are often used to meet timing specification. Tabbed routing is newly proposed to improve the route channel utilization However, the signal integrity impact is required to be evaluated.

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iModeler: Fast PDK Model Generation

A process design kit (PDK) is a set of files used within the semiconductor industry to model a fabrication process for the design tools used to design an integrated circuit. With a PDK, designers can jump-start chip design and work through the design flow seamlessly, from schematic entry to tapeout. PDK accuracy is essential for RFIC designs and increase the chances of first-pass successfully silicon. Cadence Virtuoso based schematic and layout flow is widely adopted for RF designs. iModeler allows PDK engineers to stay in Cadence Virtuoso design environment to easily create the parameterized cells (PCells), accurate parameterized equivalent circuit SPICE model, symbols and technology files. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves PDK generation efficiency. Artificial Neural Network (ANN) based synthesis flow provides an efficient way to synthesize the passive components with +/-5% for 90% of samples, and greatly help IC designers to reduce the design cycles and achieve first-pass silicon success.

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CableExpert: Fast and Accurate Cable Modeling and Simulation

Cable assembly is a key component in network systems. Accurate modeling of cables is becoming a necessity to achieve the desired signal integrity with multi-gigabit data rate. Twinaxial cable used for SFP and QSFP interface in 10G/40G/100G Ethernet is such an example. Many parameters have significant impact on signal quality such as drain type and shielding pattern, to name a few. Engineers need a fast and accurate way to model and simulate the cable with high confidence in signal integrity.

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IRIS Plus: Fast RFIC and MMIC Passive Extraction simulation tool

Xpeedic IRIS Plus provides a 3D EM simulation tool of passive devices and interconnect structures for RF/microwave chips, modules, packages, and circuit boards. Industry leading multi-layer structure of the method of acceleration technology, fast and accurate simulation of complex electromagnetic effects, including the skin effect of the conductor, proximity effect and multiple dielectric loss. IRIS Plus support multi-thread calculation, its solver greatly reduce the EM simulation time, improve the design efficiency. IRIS Plus support import IRIS project file, GDS, DXF file, also integrate RFIC template modeling, and RFPCB template modeling. The IRIS Plus design flow will greatly reduce the IC design time of RFIC designer.

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Hermes: High Speed PCB Signal Integrity Analysis

Impedance discontinuity in the signal path has a significant impact on signal integrity for high speed channel design. Among the many discontinuities, via discontinuity plays an important role in the high speed channel design. Three-dimensional full-wave EM simulation is constantly used to analyze via discontinuity, but there are many defects in the traditional 3D full-wave simulation, for example, the model creation is complex and time-consuming. Hermes provides a fast and accurate way to simulate PCB board and package structure of signal integrity problems, such as insertion loss, return loss, crosstalk, etc., also allows the designer to simulate and track processing for post-layout. Hybrid algorithm have a very fast speed in the premise of ensuring the accuracy of the results, which greatly improve the efficiency of the simulation. The powerful parametric sweeping function can be made by changing the properties of the pad, the stackup, the trace layer and the depth of the back hole, and the results can be easily compared with others. By using the unique electromagnetic field simulation engine, the S parameters can be extracted efficiently and accurately, and update the physical parameters such as the length, width, distance, and stackup to optimize the design. Hermes also provides the feature of exporting to HFSS, which can be used to quickly create models.

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ChannelExpert: High Speed Channel Exploration

High speed serial channel design is becoming more and more challenging because of the ever increasing data rate. At multi-gigabit per second data rate, channel designers must characterize all the pieces in the signal path from transmit to receiver including connector, via, and trace, which are typically represented by either IBIS model, AMI model, S-parameter blocks or RLGC transmission line (TML) model. Conventional SPICE-like circuit simulator has difficulty to efficiently handle the channel with mixed S-parameter and TML models, especially with large number of ports. ChannelExpert provides a fast and accurate way to address the signal integrity issue arising from the cascaded network of S-parameter blocks and TML models. Its frequency domain cascading technology and 2D RLGC full wave transmission line solver enable quick and accurate channel simulation. Its intuitive graphic interface lets you easily design, analyze and optimize your high speed serial links for compliance with design standards. Its quick channel build by table allows easy channel setup. Its parametric support enables the quick what-if analysis by sweeping the different S-parameter models for the channel element of interest. S-parameter based fast circuit solver supports the latest IBIS and AMI model, and provides the next generation modulation PAM-4 analysis flow.

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SnpExpert: S-Parameter Exploration

S-parameters, traditionally used in RF/Microwave design, are widely adopted by high speed digital designs as the multi-gigabit interface continues to advance to higher data rate. Xpeedic SnpExpert provides a quick way to understand the electrical characteristics of the passive interconnectors in a system by not only viewing the S-parameter in frequency domain but also examining the time domain reflectometry (TDR). One-click definition of differential pairs and victim/aggressor setup, together with the built-in NEXT, FEXT, PSXT, ILD, ICR, and ICN, allows user to quickly evaluate the crosstalk. The built-in delay and skew calculator requires no cumbersome circuit schematic setup. The built-in compliance metrics with IEEE 802.3ap, 802.3ba, 802.3bj, SAS, PCIe, SATA and OIF CEI 25G/28G standards quickly reveal the S-parameter compliance. The built-in passivity, causality, reciprocity, and stability metrics tell the quality of the S-parameter, and built-in enforcement algorithm fix S-parameter quality issues. The built-in template automates the process from S-parameter plotting to report in Word or PPT. The through-only de-embedding method helps SI engineers to quickly obtain the DUT characteristics by removing the fixture effect. Accurate NRZ and PAM-4 eye diagram calculation with equalization and pre-emphasis technology help user get an intuition feeling about high speed channel performance.

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