Overview

Xpeedic’s Genesis electronic system design platform includes XSCH, XPKG, XPCB , XLIB modules. Based on the concept of simulation-driven design, Genesis integrates Xpeedic’s simulation capabilities, assists the collaborative analysis of pre-middle-post-design stages, and advances the identification and resolution of multi-physics problems such as circuit, of the unified electromagnetic, power and thermal field to the early stage of design. It realizes the success solution of system design and simulation, and improves the efficiency of product research and development.

Genesis XPKG is mainly used for system-level package design with the simulation collaboration. XPKG supports chip stacking, ceramic cavity and other structure settings, and realizes RDL routing design based on requirements from the rule manager, which effectively helps customers complete complex dense layout design and meet WLP specifications. Users can also use XPKG for FCBGA, POP, PLP and other types of package designs. XPKG supports the whole process design from layout design, post-simulation to co-optimization.

Key Features

• Customized layer stacking and material parameter settings: Support self-defined stacking. It enables the creation of die stack layers with wire-bonding device pads and the display of the die stacking structure. Meanwhile, it supports material parameter editing, as well as parameter calling for the co-simulation.

• Flexible wirebond routing: Support the batch generation of wirebonds and the operations like the ring / cross-ring pushing. The pushing function can help quickly adjust the positions of the wirebond in batch by complying with the requirements of rules in order to improve the design efficiency.

• Various package types: In addition to supporting classical package design such as FCBGA, it also enables RDL, POP, PLP and other package designs.

• Editing and dynamic refresh for copper foil: It supports common copper foil operations such as interactive definition, editing and merging of dynamic copper foil.

• Complete package design rule manager and DRC: Support the layer stack setting and the rule management of electrical, physical and spacing through the rule manager. Users can manually create equal-length groups based on interconnection networks and PinPair, and finish equal-length winding and equal-length analysis functions manually. It has the function of design rule checking (DRC) and positioning according to relative rules.

• Co-simulation and data support: Support the unified data format of Xpeedic’s internal simulation platform. Users can quickly conduct the power DC analysis within the same design. The design files are imported into the internal and external simulation platforms through ODB++, IPC-2581 and other standard formats to complete the signal integrity and electro-thermal co-simulation, so as to finally realize the simulation-driven design. In addition, the optimal simulation result is output into various electrical topology rule files and sorted into the library for cross-design reuse.

• Manufacturing standard data export: Support the design to generate reports such as tear drop, residual copper rate, and design wiring state statistics. It can output RS-274X standard format light drawing, drilling, DXF, IPC356A, ODB++, IP2581, GDS and other documents required for production and manufacturing with one-click operation.