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Xpeedic Joins GLOBALFOUNDRIES RFwave Partner Program to Speed Time-to-Market for Wireless Connectivity, Radar and 5G

Cupertino, CA. — October 12, 2018 —Xpeedic Technology, Inc. and GLOBALFOUNDRIES today announced the addition of Xpeedic Technology to GF's RFwave Partner Program.

The RFwave Partner Program builds upon GF's industry-leading radio frequency (RF) solutions, such as FD-SOI, RF CMOS (bulk and advanced CMOS nodes), RF SOI and silicon germanium (SiGe) technologies. The program provides a low-risk, cost-effective path for designers seeking to build highly optimized RF solutions for a range of wireless applications such as IoT across various wireless connectivity and cellular standards, standalone or transceiver integrated 5G front end modules, mmWave backhaul, automotive radar, small cell and fixed wireless and satellite broadband.

“Xpeedic is excited to join GF's RFwaveTM Partner Program. This partnership enables our mutual customers to design RF silicon and system with confidence by adopting Xpeedic's foundry-proven EDA tools, IRIS, which has been certified in GLOBALFOUNDRIES' 22FDX® process technology, and unique passive integration solution for RF front end module design. ”said Dr. Feng Ling, CEO of Xpeedic Technology, “The RFwave program is a great platform to give RF design community access to a broad set of innovative RF solutions developed on GF's industry-leading RF technology platform by the RFwave members.”

“As the RFwave program continues to expand, partners play a critical role in helping to serve our growing number of clients and extend the reach of our RF ecosystem by providing innovative RF-tailored solutions and services,” said Mark Ireland, vice president of ecosystem partnerships at GF. “These new partners will help drive deeper engagement and enhance technology collaboration, including tighter interlock around quality, qualification and development methodology, enabling us to deliver advanced highly integrated RF solutions.”

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Xpeedic to Present at Samsung Foundry's DAC Theater

Date: June 25 Monday 3:30pm

Place: San Francisco, CA, US

As a partner of Samsung Advanced Foundry Ecosystem (SAFE) program, Xpeedic is invited to present at Samsung Foundry's DAC 2018 Theater. Dr. Feng Ling, Founder and CEO of Xpeedic, will give the presentation titled  Accurate Passive Modeling and Simulation for Advanced Process Nodes  at Samsung’s booth.

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As we move to advanced process nodes, electromagnetic simulation of passives and interconnects becomes challenging for IC designers. In the presentation, Xpeedic IRIS flow with seamless integration in Cadence Virtuoso platform will be demonstrated. At the design stage, IRIS and iModeler enable fast passive modeling and synthesis with its accelerated Method of Moments (MoM) solver engine and artificial neural network(ANN) technique. Through the collaboration between Xpeedic and Ansys, IRIS has a direct link to Ansys’s 3D Finite Element Method (FEM) based HFSS to enable passive simulation verification at the signoff stage. This link also makes the simulation of arbitrarily shaped 3D structures and IC-package co-simulation possible.

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During DAC 2018, Xpeedic will bring a series of demos covering simulation from IC, package, to system at its DAC booth# 2041, including the IRIS flow for passive modeling and simulation in advanced nodes, IRIS for both high-resistivity silicon (HRSi) and through-glass-via (TGV) based IPD design, Hermes for 3D package simulation, and expert-series signal integrity tools for high speed systems.

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We look forward to meeting you there.

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Xpeedic's IRIS Certified for EM Simulation in GF 22FDX Process

Cupertino, CA. — June 12, 2018 —Xpeedic Technology, Inc. today announced that its 3D full-wave electromagnetic (EM) simulation tool, IRIS, has been certified in GLOBALFOUNDRIES' 22FDX® process technology. This certification enables designers to run IRIS with confidence using the certified IRIS process file available in GF's 22FDX PDK.

Xpeedic's IRIS is empowered by an accelerated Method of Moments solver engine to achieve both accuracy and scalability for large-scale structures. For advanced nodes, it takes into account the width- and spacing-dependent process variations such as resistance table and bias table. As a result, IRIS is able to capture the conductor skin effect and proximity effect to accurately simulate passive components like inductors and MOM (metal-oxide-metal) capacitors. Xpeedic has done extensive simulation on various inductors and MOM capacitors with different process stack options. Excellent correlation with silicon measurement has been achieved.

“We are very pleased that IRIS is able to achieve excellent correlation with measurement and thus certified for GF's 22FDX process,” said Dr. Feng Ling, CEO of Xpeedic Technology, “With its powerful EM solver engine and seamless integration in design environment, IRIS can greatly help IC designers to shorten the design cycles and achieves first-pass silicon success.”

The electromagnetic certification program by GF ensures that every EM tool certified by the program meets the highest quality standards. With this certification, IC designers can choose their preferred EM simulation tool and its corresponding process file to ensure their design confidence and reduce time-to-market.

Xpeedic 2018_JobQueue

EDA Release – New Upgrade – JobQueue 2018

We are glad to announce that Xpeedic released the simulation job queue system —— JobQueue 2018 this month.

JobQueue 2018 is an industry-leading simulation job management platform with dynamic allocation of computing resource, validity checking, HPC/PBS, and real-time display of simulation results to improve tool usage.

What's new in JobQueue 2018

  • Support both local and distributed run when submit simulation job.
  • Supported to configure HFSS project validation checking rules, and supported setting with each queue.
  • Supported to display job stat information of queue.
  • Supported to configure memory limitation of node.
  • Supported to set priority of job.
  • Supported to delete completed job by system administrator.
  • Supported to set max job submitted by user.
  • Added abstract information of job on usable queue on submition page, and display queue loading by different color.
  • Try to submit HFSS job automatically if error occured on checking license.
  • Supported to display node resource of job.
  • Supported to submit single frequency HFSS project job.
  • Optimized job time information on list, add job simulation duration column.
  • Added job status for waiting for license after submited.
  • Added getting error message of simulation and display on error information page.
  • Supported queue number of job on none-cluster job system.
  • Supported to search job by node address.
  • Added operation system exception detecting and handling.
  • Added to detect simulation started out of system.
  • Added warning and comfirming if user try to leave page before submitted job.
  • Optimized rule of generating job data directory.
Xpeedic 2018_SnpExpert

EDA Release – New Upgrade – SnpExpert 2018

We are glad to announce that Xpeedic released the S-parameter Exploration —— SnpExpert 2018 this month.

SnpExpert 2018 is a widely-adopted S-parameter exploration tool. It integrates all the S-parameter post-processing functions, and supports Python automation, DFE/CTLE auto-optimization, and new addition of 56Gbps and COM compliance.

What's new in SnpExpert 2018

  • Support Python script to invoke most SnpExpert features, including S-parameter import, plot, add mark, TDR, TOD and so on.
  • Support CTLE and DFE adaptive optimization and manual tuning features when plot eye diagram, also provide real time equalization preview plot to ease the tuning process.
  • Add new built-in compliances for S-parameter exploration, including OIF CEI_56G_LR_PAM4, OIF CEI_28G_VSR, IEEE 802.3cd, SAS 3.0, IEEE 802.3bz and MIPI D-PHY compliances.
  • Support parallelized COM analysis for IEEE 802.3cd, IEEE 802.3bs and IEEE 802.3by based on the latest compliance requirements.
  • Add “Apply to Cable/TML” option in TOD and halve S-parameter to improve long transmission line de-embedding accuracy and speed.
  • Add Open-Thru De-embedding (OTD) method for on-chip de-embedding.
  • Support both “Simplified ” and “Advanced” S-parameter cascading to accommodate difference usage scenario.
  • Support multiple data curves gating with only one click, and export the whole S-parameter after gating.
  • Support FFT_Mag(), FFT_dB(), FFT_Imag() and FFT_Real() functions for time domain data sources.
  • Support PhaseDelay() and PhaseDelayDiff() to calculate group delay of both single-ended and differential S-parameter.
  • Support horizontal line when add markers to measure delay and skew value.
  • Explicit output PASS/FAIL information for “Channel” and “Template Plot” based on compliance limit.
  • Support global variable definition and recursive invoke to better reuse between different data sources.
  • Add S, Y, Z and RF template quick plot panel in SnpExpert main window.
  • Support both single-ended and differential NEXT/FEXT/THRU S-parameter export when split S-parameter file with large number of ports.
  • Support S-parameter plot with odd number of differential pairs.
  • Support opening SnpExpert project by double click.
  • Save project status and user settings when software encounter abnormal situation.

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Xpeedic 2018_ViaExpert

EDA Release – New Upgrade – ViaExpert 2018

We are glad to announce that Xpeedic released the 3D Via Modeling and Simulation —— ViaExpert 2018 this month.

ViaExpert2018 is an industry-leading via modeling and simulation tool. It supports remote and distributed simulation that are managed by Xpeedic Distributed Processing Management(XDPM), manual wiring, and Keepout parameterized library and CMF/SMP modules to provide better solutions for design optimization of 56Gbps and higher speed system.

What's new in ViaExpert 2018

  • Support HPC, remote and local simulation under the management of XDPM (Xpeedic Distributed Processing Management) module to maximize high computing machine availability.
  • Unify simulation jobs submit and status monitor flow in “Submit Job” and “Job Manager” to support more user-friendly and real-time feedback batch run.
  • Support arbitrary parameterized keepout definition, management and usage in 2D footprint window to explore the optimal antipad geometry. The keepout shape can be defined by the unite of lines/arcs or regular parameterized geometries.
  • Adjust 2D footprint window features to “Footprint” page and categorized as “Via”, “Trace”, “Port” , “Keepout” and “Component” to give user intuitive and convenient operation links.
  • Support single-ended and differential manual routing with obstacle avoidance capability.
  • Support arbitrary via array define, move, duplicate, align top/bottom/left/right, distribute horizontally/vertically, undo and redo features in 2D footprint window.
    Add CMF and SMP template to quick build and explore capacitor and SMP performance.
  • Support the RLC boundary to add RLC circuits in serials or in parallel, also mark RLC boundary position for both 2D/3D view if added.
  • Add “Material Library” module to unify frequency dependent material define, modify, export and re-use flow across different projects, and even different teams. 
    Support showing or hiding metal layers in the 2D footprint window.
  • Support parametric of layer thickness, trace width with multiple segments for both template and layout flow and combined anti-pad, also export parameterized parameters to HFSS.
  • Code-level integration of SnpExpert basic S-parameter and TDR plot features to give user more user-friendly flow to explore simulation results.
  • Support easy and efficient Allegro to ViaExpert plugins, export allegro layout to ViaExpert with only one-click based on net selection.
  • Support opening ViaExpert project by double click.
  • Automatically save ViaExpert project status and user settings at user defined interval.

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Xpeedic 2018_iModeler

EDA Release – New Upgrade – iModeler 2018

We are glad to announce that Xpeedic released the passive PDK Model Generation —— iModeler 2018 this month.

iModeler 2018 provides RFIC designers a fast solution for RF passive design in Cadence Virtuoso platform. The solution employs a full-wave 3D EM solver with both multi-core and distributed parallelization feature that greatly reduces the EM simulation time. It includes several types of tools for modeling and parameter extraction which can deal with most cases. This software will make RF passive device design easier and increase the efficiency.

What's new in iModeler 2018

  • Support bias table and rho table in iModeler to account for technology variations for advanced IC nodes.
  • Support PCell synthesis database buildup based on Artificial Neural Network (ANN) algorithm for PDKtoModel flow.
  • Add interleave transformer and splayed inductor templates to quick create PCell and parameterized equivalent circuit.
  • Support create PCell only flow without run EM simulation.
  • Support Equivalent Circuit generation for each new iCell generated from sweep table.
  • Add “Abort All” button to stop iModeler batch EM simulation defined in sweep table.
  • Reduce iModeler simulation options to simplify IRIS usage and give better user experience.
Xpeedic 2018_IRIS

EDA Release – New Upgrade – IRIS 2018

We are glad to announce that Xpeedic released the RFIC Passive Extraction —— IRIS 2018 this month.

IRIS 2018 obtained the GF 22FDX process certification, provides a 3D fast EM simulation tool integrated in Cadence Virtuoso design flow. The fast 3D method of moments solver with both multi-core and distributed parallelization greatly reduces the EM simulation time thus improves the design efficiency. The seamless integration with Virtuoso not only enables designers to stay in the Cadence design environment to perform the EM simulation which avoids the manual and error-prone layout data conversion, but also realizes the perfect convergence to front-end for design verification by automatic back-annotation.

 What's new in IRIS 2018

  • Support bias table and rho table in IRIS to account for technology variations for advanced IC nodes. 
  • Improve via merge efficiency with 10x speedup for large scale via arrays and make via merge one-time operation to save re-run overhead.
  • Support IRIS export to HFSS 3D Layout with tuned simulation settings to ensure accuracy as part of Xpeedic and Ansys software partnership.
  • Unify IRIS2HFSS and IRIS2HFSS3DLayout flow to simplify IRIS simulation project export usage.
  • Support automated port search and define feature based on pre-defined pin position.
  • Support Synopsys StarRC Interconnect Technology Format (*.itf) and IRIS Technology (*.lyr) conversion.
  • Reduce IRIS simulation options to simplify IRIS usage and give better user experience.

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